AMBA AHB and APB

In short: AMBA AHB is a high-bandwidth, pipelined system bus for CPUs, DMA and memory controllers, while APB is a simple, low-power, unpipelined bus for slow peripherals — and an AHB-to-APB bridge stitches the two domains together.

If you have ever opened a block diagram of an ARM-based SoC, you have seen the AMBA (Advanced Microcontroller Bus Architecture) family at work. Two of its oldest and most widely taught members — AHB (Advanced High-performance Bus) and APB (Advanced Peripheral Bus) — still underpin the interconnect in microcontrollers from Cortex-M0 parts up to the control planes of large application processors. This article explains what each bus does, why they coexist, how pipelining gives AHB its throughput, and how the bridge between them actually works.

Why two buses instead of one?

The core idea behind AMBA is a classic engineering tradeoff: a fast bus is expensive, and a cheap bus is slow. Rather than force every block onto one compromise, ARM split the system into a high-performance domain and a peripheral domain.

The CPU, on-chip SRAM, a DMA controller and a flash/DRAM controller all push hundreds of MB/s and need back-to-back transfers. Putting them on AHB — a pipelined bus with burst support — keeps them fed. A UART, a GPIO block, a watchdog timer or an I²C controller, by contrast, might be accessed only a few thousand times a second. Wiring those onto the fast bus would waste gates (every slave must decode the full AHB handshake) and burn dynamic power. They live on APB instead.

Key fact: APB has no pipeline and no bursts. Every APB access is exactly two cycles — a SETUP phase and an ACCESS phase — which is why it is cheap to implement and easy to verify, but caps out far below AHB throughput.

How AHB pipelining works

AHB's throughput advantage comes from overlapping the address phase of one transfer with the data phase of the previous one. While the slave is driving read data (or latching write data) for transfer N, the master is already presenting the address and control signals (HADDR, HWRITE, HSIZE, HBURST) for transfer N+1. This two-stage pipeline means that in steady state a new word moves every clock, not every two.

The handshake is governed by HREADY. A slave that needs more time asserts HREADY=0 to insert wait states, and reports status on HRESP (OKAY or ERROR). Bursts are described by HBURST — SINGLE, INCR, or fixed-length wrapping bursts like WRAP4/INCR8/WRAP16 — which let a cache line be fetched as one indivisible sequence, exactly what you want for a Cortex-M cache refill or a DMA scatter-gather.

Key fact: At 100 MHz with a 32-bit AHB data bus running zero-wait-state INCR bursts, you reach ~400 MB/s. The same clock on APB, at two cycles per access, delivers at best ~200 MB/s and in practice far less because peripheral accesses are sparse and often wait-stated.

The APB state machine

APB is deliberately dumb. Each transfer walks through three states: IDLE → SETUP → ACCESS. In SETUP the bridge drives PADDR, PWRITE, PWDATA and asserts PSEL for the chosen slave. On the next clock it raises PENABLE, entering ACCESS, and the slave completes using PREADY (added in APB4/APB3 to allow wait states) and flags errors on PSLVERR. There is no pipelining and no burst concept — simplicity is the point, because a UART simply does not need 400 MB/s.

What the bridge actually does

The AHB-to-APB bridge is itself an AHB slave on one side and the sole APB master on the other. Its jobs are: decode which peripheral an AHB address targets and generate the right PSEL; translate AHB's pipelined, possibly-bursting protocol into APB's two-phase accesses; and hold HREADY low on the AHB side for the extra cycles APB needs, so the fast bus stalls gracefully instead of corrupting data. Because APB accesses take at least two cycles and AHB expects one, the bridge is where the two clock-rate and timing worlds are reconciled. Many SoCs also use the bridge point to cross clock domains, running APB slower than AHB to save power.

AHB vs APB at a glance

Where this sits versus AXI

For modern high-throughput subsystems, ARM introduced AXI, which goes beyond AHB's single in-flight pipeline with independent read/write channels, out-of-order completion and ID-based transaction tagging. A practical SoC often uses all three: AXI for the DRAM/GPU/accelerator mesh, AHB-Lite for a Cortex-M control fabric, and APB behind a bridge for housekeeping peripherals. If you want the deeper comparison, read our companion piece on the AXI protocol explained, and the bridging mechanics overlap with what we cover in AHB arbitration and multilayer interconnect.

In verification practice you will exercise these buses with vendor VIP — Synopsys VC Verification IP, Cadence's AMBA UVC library, or Siemens Questa VIP — driving constrained-random AHB/APB traffic against your DUT and checking protocol compliance with built-in assertions. Teams building their own IP often validate the bridge FSM first because that is where most protocol-translation bugs hide.

Want to design and verify an AMBA interconnect hands-on, from RTL to UVM testbench? The CourseTron protocol and verification track walks you through AHB, APB and AXI with real labs. For industry design-services support, our partner Avecas VLSI design services works with these fabrics on production silicon.

Frequently asked questions

Why is every APB transfer two cycles?

The protocol splits each access into a SETUP cycle (address and control asserted, PSEL high) and an ACCESS cycle (PENABLE high, slave responds). This two-phase handshake removes the need for combinational timing closure on the peripheral and makes slaves trivially simple to build and verify.

Can AHB have more than one master?

Full AHB supports multiple masters through an arbiter that grants the bus and manages HBUSREQ/HGRANT. The lighter AHB-Lite variant, common in Cortex-M, assumes a single master and drops the arbitration logic to save area.

Does the bridge slow down the CPU?

Only for peripheral accesses. The bridge asserts HREADY=0 on AHB while the APB side completes its two-plus cycles, so the CPU stalls for those few cycles. Since peripheral accesses are rare compared with memory traffic, the overall performance impact is negligible.

Is AHB obsolete now that AXI exists?

No. AHB-Lite remains the standard control fabric in Cortex-M microcontrollers because it is simpler and smaller than AXI. AXI is used where its channel parallelism and out-of-order features actually pay off, such as DRAM and accelerator traffic.