In short: An FPGA gigabit transceiver (GT) is a dedicated full-duplex SerDes hard block that serializes parallel data up to tens of Gb/s per lane, recovers the clock from the data stream with a CDR, equalizes a lossy channel, and can bond several lanes into one wide link for protocols like PCIe, Ethernet, and Aurora.
If you have ever wondered how a single FPGA pin pair carries 25 Gb/s across a backplane with no separate clock wire, the answer is the gigabit transceiver. These GTs are among the most complex hard blocks on a modern device, and understanding them is a reliable way to stand out in a high-speed digital or SoC interview. Let us walk through what actually happens inside one.
Why a hard block, and not fabric logic?
At 1 Gb/s a bit is 1 ns wide; at 28 Gb/s it is roughly 36 ps wide. FPGA fabric flip-flops simply cannot toggle that fast, and routing single-ended CMOS at those rates would radiate and fail. So vendors drop in a mixed-signal hard macro: AMD/Xilinx calls these GTH/GTY/GTM, Intel/Altera calls them the transceiver tiles (e.g. the E-tile and P-tile). The fabric hands the GT a wide parallel word (say 32, 64, or 128 bits) at a comfortable fabric clock, and the GT does the fast serial work in dedicated analog and custom logic.
Numbers that matter: A GTY lane runs to about 32.75 Gb/s. A 64-bit internal datapath at 32 Gb/s means the fabric only needs a 500 MHz parallel clock (32e9 / 64), which standard logic handles easily.
The transmit path: parallel in, serial out
On the TX side the parallel word first passes through an encoder (8b/10b, 64b/66b, or 64b/67b for modern links) to guarantee enough transitions for clock recovery and to keep the signal DC-balanced. A parallel-load shift register — the actual "serializer" — then clocks the bits out one at a time against a high-speed serial clock produced by an on-chip LC PLL. Finally a feed-forward equalizer (FFE / pre-emphasis) de-emphasizes low-frequency content so that, after the channel attenuates the high frequencies, the eye opens back up at the far end.
Clock and data recovery (CDR): the clever bit
There is no forward clock on a serial lane, so the receiver must extract timing from the data edges themselves. A CDR uses a phase detector (commonly a bang-bang / Alexander detector that samples at the edge and the centre of each bit), a loop filter, and a phase interpolator or VCO to lock a sampling clock to the incoming eye. This is why line encoding matters: 64b/66b guarantees a transition at least every 66 bits so the CDR never drifts during long runs of identical bits. If the CDR loses lock, you see bursts of errors — a classic debug symptom.
Equalization: fighting the channel
A FR-4 backplane trace at 25 Gb/s can lose 20–30 dB at Nyquist. The GT compensates with three cooperating equalizers: TX FFE (pre-emphasis), RX CTLE (a continuous-time linear equalizer that boosts high frequencies), and RX DFE (a decision-feedback equalizer that cancels post-cursor inter-symbol interference using already-decided bits). Vendor tools auto-adapt these taps, but you still specify starting values; serial-link simulators from Synopsys (HSPICE), Cadence (Sigrity/Clarity), and Siemens (HyperLynx) are used to model the channel and verify the eye before board spin.
Line rates and PAM4
NRZ (two levels, one bit per symbol) runs comfortably to ~28 Gb/s. Beyond that, signal integrity forces a move to PAM4, which encodes two bits per symbol across four voltage levels, so 56 Gb/s needs only 28 Gbaud of bandwidth. The cost is a tighter eye (three stacked eyes with ~1/3 the vertical margin) and mandatory forward-error correction. AMD GTM and Intel P/E-tiles support PAM4 for 112G-class links.
| Class | Max rate/lane | Modulation | Typical use |
|---|---|---|---|
| GTH (UltraScale) | ~16.3 Gb/s | NRZ | PCIe Gen3, 10GbE |
| GTY (UltraScale+) | ~32.75 Gb/s | NRZ | PCIe Gen4, 25GbE, Aurora |
| GTM / P-tile | ~58–112 Gb/s | PAM4 | PCIe Gen5/6, 100/400GbE |
Channel bonding: many lanes, one link
Protocols like PCIe (x4, x8, x16) and 100G Ethernet (4×25G) stripe one logical stream across several physical lanes. Because each lane has its own CDR, the lanes arrive with different latencies (lane-to-lane skew). Channel bonding solves this: the transmitter inserts alignment/comma characters periodically, and the receiver uses an elastic buffer plus a shared bonding master to deskew all lanes to a common reference before handing the reassembled word to the fabric. Get the bonding sequence or the shared PLL wrong and the link comes up per-lane but never aligns — another frequent lab headache.
What interviewers actually probe
- Why line coding is mandatory (transition density for CDR, DC balance, run-length limits).
- The difference between CTLE and DFE, and why DFE cannot cancel pre-cursor ISI.
- How the reference clock PLL and the per-channel CDR interact, and what "QPLL vs CPLL" means on AMD parts.
- Why PAM4 needs FEC and how its SNR penalty (~9.5 dB vs NRZ) drives the move.
For a ground-up refresher on serialization theory before you tackle GTs, start with our SerDes basics primer, then move to PCIe link training on FPGAs to see bonding and equalization in a real protocol. Teams building production high-speed boards often pair FPGA bring-up with signal-integrity support from a dedicated VLSI and board design services partner.
Ready to bring up a 25G link yourself? Our hands-on FPGA high-speed I/O track walks you through GT wizard configuration, eye scans, and IBERT debug on real hardware. Explore it on the CourseTron courses page.
Frequently asked questions
Can I build a gigabit SerDes in FPGA fabric instead of using a GT?
Only at low rates (a few hundred Mb/s) using OSERDES/ISERDES primitives on regular I/O. True multi-gigabit links above ~1.25 Gb/s require the dedicated GT hard block for its PLL, CDR, and equalizers.
What is the reference clock for and why must it be so clean?
The GT's PLL multiplies an external reference (typically 100–322 MHz) up to the serial rate. Reference jitter translates directly into transmit jitter and shrinks the receive eye, so a low-phase-noise oscillator is non-negotiable on fast lanes.
Why does my link train per-lane but fail to bond?
Usually a mismatched or missing alignment/comma sequence, lanes driven from different PLLs, or lane-to-lane skew exceeding the elastic buffer depth. Confirm a shared bonding master and matched clocking across the lane group.
NRZ or PAM4 for my design?
Use NRZ up to about 28 Gb/s for simpler equalization and no mandatory FEC. Choose PAM4 only when you need higher throughput over the same channel bandwidth and can budget for FEC latency and the tighter eye.