In short: The PCIe Link Training and Status State Machine (LTSSM) is the Physical Layer state machine that takes two freshly powered devices from electrical idle through Detect, Polling, Configuration and L0, negotiating the common link width and the highest mutually supported data rate using ordered sets before any TLP ever crosses the link.
Every PCIe link you have ever used — an NVMe SSD, a GPU in an x16 slot, a 100 GbE NIC — came up because a tiny, deterministic state machine inside each device's Physical Layer walked a precise sequence of states and exchanged training patterns with its neighbour. That state machine is the LTSSM. If you are interviewing for a SerDes, verification, or PHY integration role, "walk me through LTSSM" is almost guaranteed, so let us build a real mental model rather than memorising a bubble diagram.
Why a state machine at all?
When a system powers on, the two ends of a PCIe link know almost nothing about each other. How many lanes are physically connected and functional? What is the fastest speed both sides can run — Gen1 (2.5 GT/s), Gen2 (5 GT/s), Gen3 (8 GT/s), Gen4 (16 GT/s), Gen5 (32 GT/s), or Gen6 (64 GT/s with PAM4)? Are the lanes polarity-inverted or reversed on the PCB? Receivers must recover a clock, align to symbol boundaries and de-skew lanes against one another. None of this can be assumed; all of it must be discovered through a handshake. The LTSSM is that handshake, formalised so both vendors' silicon agree bit-for-bit.
LTSSM transitions are driven by Ordered Sets — special non-data symbol groups. The two workhorses are TS1 and TS2 (Training Sequence 1 and 2), each 16 symbols carrying link number, lane number, requested data rate and configuration bits.
Detect: is anything plugged in?
The link starts in Detect, entered on fundamental reset. The transmitter performs receiver detection: it changes the common-mode voltage on each lane and watches the RC charging slope. A connected receiver presents a known termination (≈50 Ω to ground), so the rise time differs measurably from an open lane. This is pure analog electrical sensing — no symbols yet. If one or more receivers are detected, the LTSSM moves to Polling; otherwise it loops in Detect, which is why an empty slot simply sits quiet.
Polling: lock to the bit stream
In Polling both sides transmit TS1 ordered sets at the lowest data rate (2.5 GT/s). The receiver's CDR (clock-and-data-recovery) PLL locks onto the incoming edges, the elastic buffer absorbs the ppm clock difference between the two reference clocks, and symbol alignment is achieved using the comma character in the 8b/10b code (or the Sync Header / block alignment in 128b/130b encoding at Gen3+). Polling.Compliance is a side-path used by compliance test equipment to emit defined patterns on a scope. Only once bit lock and symbol lock are stable, and the devices have exchanged TS1 then TS2, does the link advance to Configuration.
Configuration: width and lane order
This is where the negotiated width is decided. The downstream port (nearer the Root Complex) assigns a Link Number and Lane Numbers inside TS1/TS2. A device advertised as x16 but sitting in an x8 slot, or with two broken lanes, will converge to the largest workable width — x8, then x4, then x2, then x1. Lane reversal (lane 0↔15) and polarity inversion are also resolved here, letting board designers route traces for signal integrity rather than pin order. When both sides echo matching TS2 ordered sets, Configuration completes and the link enters L0.
Notice that the link first reaches L0 at Gen1 (2.5 GT/s) regardless of the target speed. A Gen5 link does not start at 32 GT/s — it reaches L0 slowly, then re-negotiates upward through Recovery.
L0 and the climb to full speed via Recovery
L0 is the fully operational state: TLPs and DLLPs flow, flow-control credits are exchanged, the Data Link Layer brings the link to DL_Active. To actually hit the advertised speed, the LTSSM transitions to Recovery. Both ends advertise their supported rates in TS1/TS2; they agree on the highest common rate, the transmitters change their serialiser frequency, and — critically for Gen3 and above — run equalization. At 8 GT/s and beyond the channel loss is severe (tens of dB), so the transmitter's FFE (feed-forward equaliser) coefficients and the receiver's CTLE/DFE are tuned through the Recovery.Equalization phases (Phase 0–3) where the receiver requests specific preset/coefficient changes until the eye is open enough to meet the target BER (typically 1e-12, or 1e-6 pre-FEC at Gen6). Only then does the link run at full rate.
Low-power and exit states
| State | Purpose | Exit latency (typical) |
|---|---|---|
| L0 | Fully active, data flowing | — |
| L0s | Fast idle, single direction | < 1 µs |
| L1 | Deeper idle, PLL may be off | a few µs |
| L2/L3 | Aux power / off; needs full re-train | ms (back through Detect) |
| Recovery | Re-train, change rate, re-EQ | < ~1 ms |
A link that keeps bouncing into Recovery under load is a classic signal-integrity symptom: marginal equalization, a lossy connector, or crosstalk is pushing the BER past threshold, forcing re-training. Engineers debug this by reading the LTSSM state and error counters from the PHY — a flow you practise in our PCIe Physical Layer deep-dive and our Gen3–Gen5 equalization walkthrough.
How this is built and verified in practice
You rarely write an LTSSM from scratch — it ships as hardened controller + PHY IP. Synopsys DesignWare and Cadence both provide PCIe controller/PHY subsystems where the LTSSM is pre-verified silicon; the integrator's job is to wire the PIPE interface, configure supported rates, and close timing. On the verification side, a UVM VIP (Synopsys VC VIP, Cadence Verification IP, or Siemens/Mentor QVIP) models the far end: it drives TS1/TS2, forces lane reversal, injects errors to prove Recovery triggers, and asserts that the DUT's LTSSM reaches L0 at the correct width and rate. In the lab you watch the same states on a protocol analyser (Teledyne LeCroy, Keysight) that decodes ordered sets live. If you want hands-on RTL and UVM exposure to exactly this, our friends at ChipXpert's VLSI training run protocol-verification labs, while Avecas design services handle production PCIe PHY integration.
Ready to master link training end to end — ordered sets, equalization, and VIP debug? Explore the full protocol track on our CourseTron courses page.
Frequently asked questions
Why does a PCIe link always come up at Gen1 first?
Every receiver, regardless of generation, is guaranteed to lock at 2.5 GT/s with simple 8b/10b, so starting there gives a robust common baseline. The link reaches L0, then both ends negotiate and equalize upward through Recovery to the highest mutually supported rate.
What is the difference between TS1 and TS2 ordered sets?
Both are 16-symbol training sequences carrying link/lane numbers, the advertised data rate and configuration bits. TS1 is sent while a device is still proposing parameters; TS2 is sent once it has accepted the configuration. Seeing matching TS2 from both sides is the handshake that lets Polling or Configuration complete.
My link trained to x4 instead of x16 — why?
During Configuration the LTSSM converges to the largest width that is physically connected and passes receiver detection on every lane. Broken solder joints, an open lane, a shorter mechanical slot, or a bifurcation setting will all drop the negotiated width. Read the Link Status register to see the negotiated width and speed.
Is the LTSSM part of the Physical Layer or the Data Link Layer?
The LTSSM lives in the logical Physical Layer. It brings the electrical link up and hands a working lane set to the Data Link Layer, which then runs its own state machine (DL_Inactive → DL_Init → DL_Active) to exchange flow-control credits before transaction traffic begins.