SR Flip Flop

In short: The SR flip-flop is the simplest bistable memory element — built from two cross-coupled NAND or NOR gates — that latches a single bit using Set and Reset inputs, with one input combination (S=R=1 for NOR, S=R=0 for NAND) being forbidden because it drives both outputs to the same level and leaves the next state unpredictable.

Every register, counter, and cache cell in a modern SoC traces its lineage back to one deceptively small circuit: the SR (Set–Reset) latch. If you understand exactly why two gates feeding each other can "remember" a bit — and why one input pattern is outlawed — you understand the seed of all sequential logic. This is also why the SR flip-flop appears in almost every VLSI and digital-design interview: it exposes whether a candidate really grasps feedback, metastability, and state, or has merely memorized truth tables.

What "sequential" actually means here

Combinational logic (AND, OR, MUX, adders) produces outputs that depend only on the present inputs. A flip-flop breaks that rule: its output depends on both the present inputs and its stored history. That memory comes entirely from feedback — the output of one gate is wired back into the input of the other. The circuit settles into one of two stable states and holds it with no clock and no capacitor, purely through gate regeneration.

Core idea: Two gates in a loop form a bistable element. "Bistable" means two self-reinforcing stable points (Q=0 and Q=1). It takes a deliberate input pulse to flip from one to the other — that is storage.

The NOR implementation (active-HIGH)

The classic SR latch uses two cross-coupled NOR gates. Output Q is driven by one NOR, Q̄ (Q-bar) by the other, and each output loops back to the opposite gate's input. Because a NOR output is HIGH only when both inputs are LOW, the behaviour is active-HIGH: you assert a logic 1 on S to set, or a 1 on R to reset.

Trace it: assert S=1, R=0. The lower NOR sees a 1, so Q̄ goes LOW. That LOW feeds the upper NOR, which now sees R=0 and Q̄=0, so Q goes HIGH. Drop S back to 0 and nothing changes — Q=1 feeds back and keeps Q̄=0, which keeps Q=1. The bit is latched. Reset (R=1) does the mirror-image thing, forcing Q=0.

The NAND implementation (active-LOW)

Swap the NOR gates for NAND gates and you get the S̄R̄ latch, the configuration you most often see inside real standard-cell libraries and as the front end of a gated D-latch. A NAND output is LOW only when both inputs are HIGH, so the inputs are active-LOW: a 0 on S̄ sets, a 0 on R̄ resets. The "hold" state here is S̄=R̄=1, and the forbidden state is S̄=R̄=0. Two inverters on the front turn it back into an active-HIGH interface when needed.

Why NAND dominates silicon: In CMOS, a 2-input NAND needs series NMOS / parallel PMOS and is both smaller and faster than the equivalent NOR (NOR stacks slow PMOS in series). Cell libraries from Synopsys and foundry PDKs therefore build latches around NAND, which is why the active-LOW S̄R̄ form is the one you meet in real netlists.

Truth table and the invalid state

Here is the behaviour of the active-HIGH NOR latch. Q_next is the state after the inputs are applied; Q is the current state.

Look at the last row. With S=R=1, both NOR gates see a HIGH input, so both outputs are forced to 0 at once. That already violates the defining promise of a flip-flop — that Q and Q̄ are always complements. Worse is what happens next: if S and R are released to 0 at nearly the same instant, both gates try to go HIGH simultaneously, and the final resting state depends on tiny, uncontrollable propagation-delay mismatches between the two gates.

This is the race condition, and in physical silicon it can push the latch into metastability — a quasi-stable balance point where Q hovers near V_DD/2 for an unbounded time before randomly resolving. Static timing tools (Synopsys PrimeTime) and characterization flows (Siemens Solido, Cadence Liberate) model this with setup/hold windows and MTBF curves precisely because a metastable event propagating into downstream logic is a real, measurable failure mode in multi-clock-domain designs.

Watch the forbidden state in motion

Interview-ready distinction: A latch is level-sensitive (transparent while enabled); a flip-flop is edge-triggered. The bare SR cell above is a latch. Add an enable/clock gating stage and it becomes a gated SR latch; two such stages in a master–slave arrangement make a true edge-triggered flip-flop.

Fixing the forbidden state: the path to JK and D

Engineers did not tolerate an illegal input for long. The JK flip-flop solves it by feeding the outputs back into the input gating so that the old S=R=1 combination becomes a defined toggle operation instead of a race. The D flip-flop takes the opposite approach — it ties R to the inverse of S, making the two inputs structurally incapable of both being asserted, which is why the D-FF is the universal workhorse of synchronous RTL and the cell your synthesis tool infers from every always @(posedge clk) block. Understanding the SR latch first is what makes those two refinements obvious rather than magical.

If you want hands-on labs that build these cells in a real standard-cell flow and simulate the metastability window, our digital electronics and VLSI course track walks through it gate by gate. Teams training engineers at scale often pair this foundation with the industry programs at ChipXpert VLSI training.

Where SR cells still show up in practice

• Bus arbitration and debounce: A NAND SR latch is the textbook switch-debounce circuit for a mechanical SPDT contact — the latch rejects the milliseconds of contact bounce.
• Set/reset ports on D flip-flops: The asynchronous preset/clear pins on a library DFF are internally an SR mechanism.
• Interrupt and status flags: A one-shot event sets a bit; firmware reads and resets it — classic Set/Reset semantics.

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Frequently asked questions

Why is S=R=1 called the invalid or forbidden state?

Because it forces Q and Q̄ to the same logic level (both 0 in the NOR latch), breaking the complementary-output guarantee, and when the inputs are released together the next state is decided by random gate-delay mismatch rather than by design — a race that can cause metastability.

What is the difference between the NAND and NOR SR latch?

The NOR latch is active-HIGH (Set and Reset are asserted with logic 1, hold is S=R=0, forbidden is S=R=1). The NAND latch is active-LOW (asserted with logic 0, hold is S̄=R̄=1, forbidden is S̄=R̄=0). NAND is preferred in CMOS silicon because it is smaller and faster.

Is an SR latch the same as an SR flip-flop?

Strictly, a latch is level-sensitive and a flip-flop is edge-triggered. The bare cross-coupled cell is an SR latch; adding a clock/enable and a master–slave structure turns it into an edge-triggered SR flip-flop.

How do real EDA tools handle the metastability risk?

Static timing tools like Synopsys PrimeTime enforce setup/hold constraints, and characterization tools (Cadence Liberate, Siemens Solido) model mean-time-between-failure for synchronizer chains so designers insert enough flip-flop stages across clock-domain crossings to make a metastable escape statistically negligible.