JK Flip Flop

In short: The JK flip-flop is the universal, edge-triggered 1-bit memory element that fixes the SR flip-flop's forbidden state by making J=K=1 toggle the output, and the resulting race-around problem in level-sensitive designs is why every practical JK is built as a master-slave or edge-triggered cell.

If you have ever drawn a state machine, built a ripple counter, or stared at a timing diagram in a Synopsys VCS waveform viewer, you have met the JK flip-flop even if you did not call it by name. It is arguably the most instructive of the four classic flip-flops because it is the only one whose complete behaviour exercises set, reset, hold, and toggle in a single truth table. This article unpacks how it works, why the race-around problem exists, and how it is actually realised in silicon.

From SR to JK: closing the forbidden door

The simple clocked SR (Set-Reset) latch has one fatal flaw: when both S and R are asserted, the two cross-coupled NOR (or NAND) gates are driven to the same level, and when the inputs release, the final state is unpredictable — it depends on gate propagation-delay mismatch, which can be tens of picoseconds in a modern 7 nm standard cell. That is the "forbidden" or "invalid" input combination.

Jack Kilby's initials are often invoked for the "JK" name, though the more defensible story is simply that J and K were the next free letters. Whatever the etymology, the engineering move is elegant: feed the current outputs Q and Q̅ back into the input gating so that the S=R=1 case no longer latches an illegal value but instead toggles. In NAND-based terms:

• S_internal = J · Q̅ · CLK
• R_internal = K · Q · CLK

Because the feedback guarantees that only one of Q or Q̅ is high at a time, the set and reset paths can never both fire simultaneously. The illegal state is engineered out of existence.

The truth table — the heart of the device

The characteristic behaviour is captured in four rows. Q_n is the present state; Q_n+1 is the state after the active clock edge.

The single-line characteristic equation condenses all four rows: Q_n+1 = J·Q̅_n + K̅·Q_n. This equation is what synthesis tools implicitly target — when Cadence Genus or Synopsys Design Compiler maps an inferred flip-flop, it will usually pick a D-type library cell and derive the D input from exactly this expression, because standard-cell libraries rarely ship a native JK cell.

⭐ The excitation table is the truth table read "backwards": given a required transition, what J and K force it? 0→0 needs JK = 0X; 0→1 needs 1X; 1→0 needs X1; 1→1 needs X0. The X (don't-care) entries are exactly why JK-based counter design produces fewer logic gates than D-based design in hand-mapped work.

The race-around problem

Here is the subtlety that trips up most learners. Consider a level-triggered JK (a simple clocked latch, not edge-triggered) with J=K=1. While the clock is high, the output toggles. But the toggle output feeds straight back to the input — so it toggles again, and again, for as long as the clock stays high.

If the gate propagation delay is t_pd and the clock high-time is t_w, the output oscillates roughly t_w/t_pd times. With t_pd ≈ 50 ps and a clock high-phase of 2 ns, that is about 40 uncontrolled toggles. When the clock falls, the final state is whatever the oscillation happened to land on — effectively random. This is the race-around condition.

Two cures: narrow clocks, master-slave, and edge-triggering

The classic textbook fix is to make the clock pulse narrower than one propagation delay (t_w < t_pd) so only a single toggle can occur. This is impractical at scale — you cannot reliably generate a sub-50 ps pulse across a whole chip. The robust engineering solutions are structural:

• Master-slave (pulse-triggered) JK: two latches in series. The master is transparent while CLK=1 and samples the inputs; the slave is transparent while CLK=0 and copies the master. Because the feedback reaches the input only through the slave, which is frozen during the master's sampling window, the loop cannot race.
• Edge-triggered JK: built so the output can change only at the instant of a rising (or falling) clock edge. This is what you actually get from an HDL always @(posedge clk) block simulated in Siemens Questa or Synopsys VCS.

⚠️ Master-slave JKs suffer a secondary defect called ones-catching (and zeros-catching): a brief glitch on J during the master's transparent window is captured and held, even if J returns low before the edge. True edge-triggered cells avoid this, which is why modern standard-cell libraries ship edge-triggered flip-flops almost exclusively.

Where JK flip-flops actually get used

The toggle mode (J=K=1) is the workhorse. Tie both inputs high and a JK becomes a T (toggle) flip-flop that divides the clock frequency by two. Chain four of them and you have a modulo-16 asynchronous (ripple) counter — the canonical first lab exercise in any sequential-logic course. In synchronous counter design, the excitation table's don't-care entries let a Karnaugh-map reduction collapse the next-state logic dramatically compared with the fully-specified D excitation table.

In contemporary RTL practice you rarely instantiate a JK by name; you describe behaviour and let the tools infer storage. But understanding JK excitation is still directly interview-relevant: questions about counter design, metastability, and the difference between latches and edge-triggered flops all trace back to this device. For a gentler companion element with a single data input, see our walkthrough of the D flip-flop, and for the counting application read the ripple counter design guide.

Teams building real silicon — such as the design-services engineers at Avecas VLSI design services — lean on edge-triggered flops precisely because the race-around and ones-catching hazards make level-sensitive and master-slave cells unsafe in high-speed clock domains.

Want to master sequential logic from latches to pipelined datapaths with lab exercises in Questa and Vivado? Explore the CourseTron Digital Electronics & VLSI courses.

Frequently asked questions

Why is J=K=1 called the toggle state?

Because the output flips to its complement on every active clock edge: 0 becomes 1, 1 becomes 0. The output feedback routes the "set" path when Q is low and the "reset" path when Q is high, guaranteeing exactly one transition per edge.

Is the race-around problem present in edge-triggered JK flip-flops?

No. Race-around only occurs in level-sensitive (and, in a different form, master-slave) designs where the output can change multiple times during one clock phase. A properly edge-triggered JK allows a single transition at the clock edge, so the feedback loop cannot oscillate.

What is the difference between the truth table and the excitation table?

The truth table maps present inputs (J, K) to the next state. The excitation table is the inverse: given a desired state transition (Q_n→Q_n+1), it tells you which J and K values produce it, including don't-care conditions that simplify counter logic.

Do synthesis tools generate JK flip-flops?

Almost never directly. Tools like Synopsys Design Compiler and Cadence Genus map inferred storage to edge-triggered D flip-flops from the target standard-cell library, deriving the D input from the JK characteristic equation when needed.