Multiplexer Tree Cascading

In short: You build an 8:1 mux from two 4:1 muxes plus a 2:1 (or a 16:1 from five 4:1 muxes) by sending the low select bits to every first-level mux in parallel and the high select bits to a final mux, or by using the high bits to drive enables instead.

Why cascade at all?

Standard-cell libraries and discrete logic families ship a handful of multiplexer sizes. You will reliably find 2:1 and 4:1 cells, and sometimes 8:1, but almost never a 16:1 or 32:1. Real designs need wide selectors constantly: a register file read port choosing among 32 registers, a barrel shifter stage, a bus arbiter, a test-mode selector. The answer is always the same: build a tree of smaller muxes. If you already understand how a single stage works, revisit our 4-to-1 multiplexer walkthrough first; everything below simply composes that block.

An N:1 mux needs log2(N) select bits. That number is the whole game. An 8:1 mux needs three select lines, a 16:1 needs four, and the question becomes: which select bits go where?

Building a 16:1 mux from 4:1 blocks

Take sixteen data inputs I0 to I15. Group them in fours. Each group feeds a 4:1 mux, so you need four first-level muxes. Their four outputs feed a fifth 4:1 mux, which produces Y. Total: five 4:1 muxes, two levels deep.

Key fact: The lower select bits (S1 S0) are wired to all four first-level muxes at once. The upper bits (S3 S2) go only to the final mux. Select value 1011 therefore means: pick input 3 inside every group, then let the second level pick group 2, giving I11.

Select-line partitioning, and why the split matters

Functionally, you can swap the roles: send S3 S2 to the first level and S1 S0 to the second, then regroup the inputs as interleaved sets (I0, I4, I8, I12 and so on). The truth table of the whole block is identical. Engineers still choose deliberately, for three reasons.

• Fan-out. Whatever bits drive the first level see a load of four mux select pins each. In a 64:1 tree built from 4:1 cells, the first-level select nets fan out to 16 cells. Buffer trees or sizing are required.
• Arrival time. Put the latest-arriving select bit on the last stage. If S3 comes from a slow comparator while S1 S0 come straight from a flop, the first level resolves early and only one mux delay remains after S3 settles. Synthesis tools like Synopsys Design Compiler and Cadence Genus do this restructuring automatically when constraints reveal the skew, but you should be able to explain it by hand.
• Data layout. If the data inputs arrive naturally as a bus of consecutive words, contiguous grouping keeps routing short.

Cascading with enables instead of a second mux level

Many mux ICs, the classic 74HC151 for example, have an enable input. When the part is disabled, its output is forced to a known level (low in the 74151 family, high-impedance in tri-state variants like the 74HC251). That gives a second way to build an 8:1: use two 4:1 muxes, drive S1 S0 into both, and use S2 to enable one of them. For a mux whose disabled output is 0, the merge is just an OR gate.

The same idea scales: a 3-to-8 decoder driven by the upper select bits can enable eight 8:1 muxes to form a 64:1, with an eight-input OR (or a wired tri-state bus) collecting the result. This is exactly how memory chip selects work, and it is why a mux tree and a decoder are two views of the same structure.

Key fact: Check the polarity and the disabled-output state in the datasheet. An active-low enable with a high-impedance disabled output needs a shared bus; one that forces 0 needs an OR; one that forces 1 needs an AND. Mixing these up is the most common bench bug in cascaded designs.

Watch the select travel

The animation below follows input I5 through an 8:1 mux built from two 4:1 muxes and a 2:1 output stage. The select code is S2 S1 S0 = 101. The low bits 01 pick the second input inside the lower 4:1 mux, and S2 = 1 tells the final 2:1 mux to take the lower branch.

Area, delay and the numbers that matter

Counting 2:1 equivalents, a 4:1 mux is three 2:1 muxes, so a 16:1 tree of 4:1 cells is 15 two-to-one equivalents, the same as a 16:1 tree built only from 2:1 cells. What changes is depth and cell choice.

In transmission-gate or pass-transistor muxes, resistance accumulates along the chain, so delay grows roughly with the square of the number of series switches. Designers insert a restoring buffer every two or three levels. Static CMOS AND-OR trees avoid that, but cost more area. Your timing report after synthesis will show the mux tree as a chain of cells; use it to see which select pin is on the critical path.

Muxes in FPGAs and synthesis tools

FPGA architects use this same cascade physically. A Xilinx 7-series slice contains four 6-input LUTs, two MUXF7 cells and one MUXF8 cell. A single LUT6 can implement a 4:1 mux (four data plus two select inputs). Two LUTs plus a MUXF7 yield an 8:1, and four LUTs plus two MUXF7 and the MUXF8 give a full 16:1 within one slice, using dedicated fast wiring. Write behavioral Verilog with a case statement or a ternary chain and Vivado, Quartus or Synopsys Synplify will map to these structures for you. In ASIC flows, Design Compiler and Genus pick between mux cells and AOI gates according to your libraries, and Siemens Questa or any simulator confirms the RTL behaves the same. For a tree you can write explicitly:

module mux16 (input [15:0] i, input [3:0] s, output y);
  wire [3:0] g;
  assign g[0] = i[{2'd0, s[1:0]}];
  assign g[1] = i[{2'd1, s[1:0]}];
  assign g[2] = i[{2'd2, s[1:0]}];
  assign g[3] = i[{2'd3, s[1:0]}];
  assign y    = g[s[3:2]];
endmodule

Teams that need this reviewed in silicon, including timing closure on wide selectors, often rely on specialists such as the physical-design group at Avecas design services.

Interview traps and quick checks

• "Implement a 4:1 mux using only 2:1 muxes." Three muxes; S0 on the first level, S1 on the second.
• "Implement any 3-variable function with a 4:1 mux." Use two variables as selects and feed the third variable (or its complement, 0, or 1) to the data inputs. This is Shannon expansion, and a close relative of the mux as universal logic technique.
• Floating enables. A tri-state mux whose enable is derived from a select bit can briefly enable both devices on a transition, producing contention. Real designs add non-overlap or use the OR-merge form.
• Glitches. A 2:1 mux can glitch when both data inputs are 1 and the select changes, because the AND-OR implementation has a static-1 hazard. Cascades inherit this.

If you are preparing for placement tests in digital design, our CourseTron digital electronics courses and the hands-on training from ChipXpert VLSI training both drill these constructs with timing exercises.

Ready to go beyond muxes? Explore the CourseTron digital design courses at /courses and practise tree building, decoders and timing analysis with guided labs.

Frequently asked questions

How many 4:1 muxes do I need for a 64:1 mux?

Twenty-one: sixteen at the first level, four at the second and one at the output. The total is (64 minus 1) divided by 3, which is 21, and the tree is three levels deep.

Which select bits should go to the first level?

Functionally either works. In practice send the earliest-arriving bits to the first level and the latest-arriving bit to the final stage so it sees only one mux delay.

When is an enable better than another mux level?

Use enables when parts are physically separate (different chips or memory banks) or when you want a tri-state bus. A second mux level is better inside synchronous logic where you want predictable timing and no contention.

Does cascading change the logic function?

No. Any partitioning of the select bits gives the same truth table. It changes only area, delay, fan-out and power.