In short: Pick a flash ADC when you need gigahertz speed, SAR when you want micropower precision up to ~18 bits, sigma-delta when you chase 24-bit accuracy at audio or instrumentation rates, dual-slope for cheap, noise-immune meters, and pipelined when you must hit 12–16 bits at 100 MSPS–1 GSPS.
Every data-converter interview eventually arrives at the same question: "You have a signal and a budget for speed, resolution and power. Which ADC architecture do you choose, and why?" The honest answer is that no single topology wins everywhere. Each trades the three axes differently, and understanding why is far more valuable than memorizing a comparison chart. This survey walks the five architectures you are expected to know cold, with the numbers and physical intuition that separate a real engineer from a flashcard.
The Resolution-Speed-Power Triangle
An ADC does one job: map a continuous voltage onto a finite set of digital codes. The three cost axes are coupled by physics. Doubling resolution (one extra bit) halves the quantization step, so comparator offset, thermal (kT/C) noise and settling error must all shrink. Pushing conversion rate higher shortens the time the circuit has to settle, forcing more bias current. That is why you almost never see a converter that is simultaneously fast, high-resolution and low-power — the architectures below are different answers to which corner you sacrifice.
Flash: Brute Force at Full Speed
A flash (or "direct") converter compares the input against every possible threshold at once. An N-bit flash needs 2N−1 comparators fed by a resistor-ladder reference, and a thermometer-to-binary encoder collapses their outputs into a code in a single clock. Because there is no iteration, latency is essentially one comparator delay — this is the only way to reach multi-gigasample rates for oscilloscope front ends and 56 Gbaud SerDes receivers.
The cost is exponential. A 6-bit flash already needs 63 comparators; an 8-bit flash needs 255. Each comparator adds input capacitance, static current and offset, so die area and power explode. That is why practical flash ADCs stop around 6–8 bits.
Rule of thumb: comparator count = 2N−1. Going from 6 to 8 bits multiplies the comparator array roughly 4× — the reason flash rarely exceeds 8 bits.
SAR: The Binary-Search Workhorse
The successive-approximation-register ADC runs a binary search using a single comparator and a capacitive DAC (charge-redistribution array). It tests the MSB first, keeps or discards it, and walks down one bit per clock cycle. An N-bit conversion therefore takes N comparison steps. With only one comparator and a mostly-switched-capacitor DAC that burns charge only during transitions, SAR is astonishingly power-efficient — modern 12-bit SAR cores hit figures of merit in the single-digit fJ/conversion-step range, which is why they dominate battery-powered sensing, IoT nodes and medical acquisition.
SAR scales gracefully to 16 and even 18 bits, but speed is limited by the DAC settling time multiplied by N steps, so single-channel SAR typically tops out in the few-MSPS to low-tens-of-MSPS range before designers resort to time-interleaving several cores.
Sigma-Delta: Trading Speed for Precision
The sigma-delta (ΣΔ) converter is the champion of resolution. Instead of resolving a precise voltage directly, it uses a coarse (often 1-bit) quantizer inside a feedback loop running at a high oversampling ratio (OSR), then a digital decimation filter extracts a high-resolution word. Two effects combine: oversampling spreads quantization noise over a wide band, and the loop's noise shaping pushes that noise up out of the signal band. A second-order modulator with OSR = 256 can deliver 20+ effective bits in audio and precision-instrumentation applications.
Why it wins on accuracy: each extra bit of resolution needs only ~4× more oversampling (for a 1st-order loop) or far less for higher-order loops — you buy resolution with clock cycles and DSP, not with matched analog components.
The trade is bandwidth and latency. The decimation filter imposes group delay, and the usable signal bandwidth is the sample rate divided by the OSR. That makes ΣΔ ideal for DC-to-tens-of-kHz work (weigh scales, temperature, audio codecs) but poor for fast, latency-sensitive control loops. Continuous-time ΣΔ designs now reach tens of MHz of bandwidth in wireless receivers, blurring the old boundary.
Dual-Slope: Slow, Cheap and Unshakeably Accurate
The dual-slope (integrating) ADC charges an integrator from the input for a fixed time T1, then discharges it with a known reference while counting clocks until it crosses zero. The count is proportional to the input, and — critically — the result is independent of the exact capacitor value and clock frequency because both cancel in the ratio. If T1 is set to a multiple of the mains period (20 ms for 50 Hz), line-frequency interference averages to zero. This is why handheld 4½-digit multimeters and panel meters still use integrating converters: cents of silicon, superb noise rejection, no need for a trimmed reference network.
The penalty is obvious: a conversion takes thousands of clock cycles, so throughput is only a handful of readings per second. It is the right answer precisely when you do not care about speed.
Pipelined: The Broadband Compromise
A pipelined ADC is a chain of low-resolution stages (commonly 1.5 bits each with digital redundancy). Each stage resolves a few bits with a sub-flash, reconstructs that estimate with a DAC, subtracts it, and amplifies the residue for the next stage. Because stages operate concurrently on successive samples, throughput equals a single stage's rate even though a given sample takes several clocks of latency to emerge. This architecture fills the gap flash cannot reach and SAR cannot run fast enough for: 12–16 bits at 100 MSPS to beyond 1 GSPS, which is exactly what cellular base stations, software-defined radio and medical ultrasound demand.
The redundancy (the ".5" bit) lets digital logic correct comparator offsets, but inter-stage gain accuracy still limits resolution, and the residue amplifiers are the dominant power and calibration burden. Characterizing the resulting INL/DNL and SNDR is standard bench work; the same mixed-signal verification flows used for custom converters in Cadence Virtuoso/Spectre are where these trade-offs get closed.
Side-by-Side
| Architecture | Typical resolution | Typical rate | Power | Sweet spot |
|---|---|---|---|---|
| Flash | 4–8 bit | 1–10+ GSPS | High | Scopes, SerDes front ends |
| Pipelined | 10–16 bit | 50 MSPS–1 GSPS | Medium-high | SDR, base stations, ultrasound |
| SAR | 8–18 bit | kSPS–tens of MSPS | Very low | IoT, sensors, portable |
| Sigma-delta | 16–24 bit | DC–few MHz BW | Low-medium | Audio, precision DAQ |
| Dual-slope | 12–18 bit | <100 SPS | Very low | DMMs, panel meters |
One subtlety worth internalizing: "resolution" in bits is not the same as accuracy. Effective number of bits (ENOB), derived from measured SNDR, is what actually matters — a nominal 16-bit pipelined part may deliver only 12–13 ENOB once jitter and distortion are counted. If that distinction is fuzzy, read our companion piece on ADC resolution explained before an interview.
Choosing in Practice
Start from the signal bandwidth and the Nyquist requirement, then layer on the resolution the application genuinely needs (not what the datasheet headline offers), and finally check the power and area budget. A 12-bit, 50 kHz pressure sensor on a coin cell is a SAR problem; a 100 MHz instantaneous-bandwidth radio is pipelined or interleaved SAR; a 0.1 Hz thermocouple wants sigma-delta. Getting this mapping right is a hiring signal — see how we drill it in our analog track and in our broader mixed-signal design fundamentals module. For hands-on fabrication-aware design services beyond training, teams often partner with Avecas VLSI design services.
Ready to master data converters from quantization noise to silicon? Explore the Analog & Mixed-Signal track on CourseTron Courses and build a SAR ADC from the comparator up.
Frequently Asked Questions
Why can't a flash ADC just add more comparators to reach 16 bits?
Comparator count grows as 2N−1, so 16 bits would need 65,535 comparators. The input capacitance, static power and offset-matching requirements become physically and economically impossible, which is why flash stays at 6–8 bits and pipelined architectures take over for high resolution at speed.
What makes sigma-delta ADCs so accurate?
They oversample far above Nyquist and use feedback to shape quantization noise out of the signal band, then filter it digitally. Resolution comes from clock cycles and DSP rather than from precisely matched analog components, so 20–24 effective bits are achievable at low bandwidth.
When would I still choose a dual-slope ADC today?
For slow, inexpensive, noise-immune measurement — digital multimeters and panel meters. By integrating over a multiple of the mains period it rejects 50/60 Hz interference, and its result is independent of absolute capacitor and clock values, giving excellent stability for cents of silicon.
Is SAR or pipelined better for a 14-bit, 10 MSPS application?
Both can work. A single SAR core is near its speed ceiling at 10 MSPS for 14 bits and will be lower power; a pipelined part delivers the rate comfortably with more power and latency. The choice hinges on your power budget and whether conversion latency matters to the control loop.