In short: An ADC's resolution in bits sets how many discrete output codes it has (2N), which fixes the step size as VREF/2N and bounds the unavoidable quantization error at ±½ LSB.
Every analog-to-digital converter faces the same fundamental problem: the input is a continuous voltage that can take infinitely many values, but the output is a finite integer. The bridge between those two worlds is resolution, expressed in bits. Resolution is the single most misunderstood ADC spec among students and junior design engineers, partly because it is routinely confused with accuracy. This article unpacks what the bit count actually buys you, how it couples to step size and reference voltage, and why quantization error is a mathematical certainty rather than a defect you can design away.
What "N bits" really means
An N-bit ADC maps its input range into 2N distinct output codes. A 3-bit converter has 23 = 8 codes (000 through 111). A 12-bit converter has 4,096 codes; a 16-bit converter has 65,536. The bit count is a measure of granularity, not of correctness. A 16-bit ADC with a badly drifting reference can be less accurate in absolute terms than a well-trimmed 10-bit part, even though it slices its range into 64× more pieces.
Key fact: Resolution tells you how finely the input is divided. Accuracy tells you how close the reported value is to the true value. They are independent axes, and real datasheets (e.g. Texas Instruments ADS1115, Analog Devices AD7124) list them as separate numbers.
Step size: the LSB
The weight of the least significant bit — the voltage change needed to move the output by exactly one code — is the step size, usually written Q or 1 LSB:
Q = VREF / 2N
This is the equation that ties resolution, reference voltage, and step size together. Everything downstream follows from it. Notice that resolution in bits is dimensionless, while step size is a voltage — the reference is what gives the bits a physical meaning.
A concrete numerical example
Take a common lab scenario: a 12-bit ADC with a 3.3 V reference, like the SAR converter inside an STM32 microcontroller.
- Number of codes: 212 = 4,096
- Step size: Q = 3.3 V / 4,096 ≈ 805.7 µV
- Any input change smaller than ~806 µV may not change the output code at all.
Now drop the reference to 1.8 V on the same converter: Q falls to 1.8/4096 ≈ 440 µV. You just improved resolution-per-volt by shrinking the range — a deliberate trick used when you know your signal never exceeds 1.8 V and you want finer discrimination. This is why reference selection is a first-class design decision, not an afterthought.
| Resolution | Codes (2N) | Step size (Q) | Dynamic range |
|---|---|---|---|
| 8-bit | 256 | 19.5 mV | 48.2 dB |
| 10-bit | 1,024 | 4.88 mV | 60.2 dB |
| 12-bit | 4,096 | 1.22 mV | 72.2 dB |
| 16-bit | 65,536 | 76.3 µV | 96.3 dB |
| 24-bit | 16,777,216 | 298 nV | 144 dB |
The dynamic-range column uses the familiar 6.02·N + 1.76 dB figure, which we derive below.
Quantization error, step by step
Because the output is forced onto a grid of discrete levels, the ADC must round every continuous input to the nearest code. The difference between the true input and the value represented by its code is the quantization error. With ideal rounding (half-LSB offset), this error is bounded:
−Q/2 ≤ eq ≤ +Q/2
If we assume the input is busy enough that the error is uniformly distributed across that ±Q/2 band, its root-mean-square value works out to Q/√12. Comparing the full-scale signal power to this noise power gives the signal-to-quantization-noise ratio for an ideal converter:
SQNR ≈ 6.02 N + 1.76 dB
Key fact: Every extra bit of resolution buys roughly 6 dB of SQNR. That is why engineers chasing a low noise floor count bits, and why "effective number of bits" (ENOB), measured from a real sine-wave test, is the honest figure once thermal noise and distortion are folded in.
Resolution versus the real world
Datasheet resolution is a ceiling, not a guarantee. A 16-bit converter whose board layout injects 200 µVrms of noise effectively delivers maybe 13 noise-free bits. When you simulate a mixed-signal front end in a tool like Cadence Virtuoso (Spectre), or verify a digital decimation filter in a Siemens Questa testbench, you quickly see that reference noise, comparator offset, and clock jitter all erode the bits you paid for. Monte Carlo analysis in Synopsys HSPICE is the standard way to confirm how many bits survive process and temperature variation before tape-out.
This is also where the choice of architecture matters: a SAR ADC, a delta-sigma modulator, and a flash converter reach a given resolution by completely different mechanisms and with different speed/power trade-offs. If you want the architectural picture, read our companion piece on the types of ADC converters, and pair it with sampling and the Nyquist theorem to understand how resolution and sample rate jointly define a data converter. Hands-on front-end design and tape-out support is something our sister team offers through Avecas VLSI design services.
Practical takeaways
- Pick VREF to match your signal's full swing — a mismatched reference wastes codes and inflates effective step size.
- Don't over-specify bits; past the point where noise dominates, extra bits only add cost and settling time.
- Always think in LSBs when reading error specs (offset, gain, INL, DNL are all quoted in LSB).
- Quantization error is inherent; dithering and oversampling reshape it but can never remove it entirely.
Want to design and verify real data converters from transistor to bitstream? Our Analog & Mixed-Signal track walks you through ADC specs, SPICE verification, and layout. Explore the CourseTron course catalog and start building silicon intuition. For live mentor-led VLSI training, see ChipXpert.
Frequently asked questions
Does more resolution mean a more accurate ADC?
Not necessarily. Resolution sets how finely the range is divided; accuracy depends on the reference stability, linearity (INL/DNL), offset, and noise. A high-resolution part with a drifting reference can report numbers with many digits that are still wrong.
How do I calculate the step size of an ADC?
Divide the reference (full-scale) voltage by the number of codes: Q = VREF / 2N. For a 10-bit ADC with a 5 V reference, Q = 5/1024 ≈ 4.88 mV per code.
Why can't quantization error be eliminated?
Because mapping an infinite continuum onto a finite set of integers always requires rounding. The best you can do is bound it to ±½ LSB and then reduce its perceived impact with techniques like dithering and oversampling, which spread or shift the error spectrum rather than deleting it.
What is ENOB and how does it relate to resolution?
Effective Number Of Bits is the resolution a converter actually achieves once real noise and distortion are included, derived from a measured sine-wave SINAD: ENOB = (SINAD − 1.76)/6.02. It is usually lower than the nameplate bit count.