In short: Phase noise and jitter are the same oscillator imperfection seen in two domains — phase noise is the frequency-domain spectral density L(f) in dBc/Hz, jitter is its time-domain integral in seconds — and both set the ultimate SNR floor of ADCs and the bit-error rate of SerDes links.
Every real oscillator drifts. Its output is never a pure tone at f0 but a slightly fuzzy spectrum, and in the time domain its zero crossings arrive slightly early or late. For an analog or mixed-signal designer, learning to move fluently between these two descriptions — and knowing which one your system actually cares about — is one of the highest-leverage skills you can build. This article connects the frequency-domain and time-domain pictures, walks through the Leeson model, and shows with concrete numbers how a clock's spectral purity decides whether your 14-bit ADC or your 32 Gb/s SerDes meets spec.
The frequency-domain view: phase noise L(f)
Model the oscillator output as v(t) = A·cos(2πf0t + φ(t)), where φ(t) is a small random phase perturbation. In the spectrum this smears the ideal delta function into skirts that fall away from the carrier. We quantify this with single-sideband phase noise, L(f), defined as the ratio of noise power in a 1 Hz bandwidth at an offset f from the carrier to the total carrier power, expressed in dBc/Hz. A good RF synthesizer might show −100 dBc/Hz at 10 kHz offset and −150 dBc/Hz at 1 MHz offset.
Rule of thumb: L(f) is reported at specific offsets. A doubling of carrier frequency through an ideal multiplier adds 6 dB (20·log10(2)) of phase noise — multiplication cannot improve spectral purity, it degrades it.
The time-domain view: jitter
The same φ(t) shows up as timing error on the clock edges. Jitter is the deviation of an edge from its ideal position, measured in seconds (or UI, unit intervals). Two flavours matter: period jitter (cycle-to-cycle variation) and phase/accumulated jitter relative to an ideal reference. For sampling systems we usually want RMS phase jitter integrated over a chosen band.
The bridge between domains is a single integral. RMS phase jitter in seconds is:
σt = (1 / 2πf0) · √( 2 ∫ L(f) df )
You integrate the (linear, not dB) phase-noise spectral density over your band of interest — say 12 kHz to 20 MHz, the classic SONET band — take the square root to get RMS radians, then divide by the carrier's angular frequency to get seconds. This is exactly what a spectrum analyzer or a tool like Keysight's phase-noise personality does when it prints "integrated jitter."
The Leeson model
The Leeson model (David Leeson, 1966) is the workhorse closed-form expression for an oscillator's phase noise. It treats the oscillator as a resonator of loaded quality factor QL inside a feedback loop with an amplifier of noise figure F. In schematic form:
L(f) = 10·log10 { (FkT / 2Ps) · [1 + (f0 / 2QLf)²] · [1 + fc/f] }
Three knobs fall straight out of it, and every one is actionable at design time:
- Signal power Ps: more power in the resonator lowers the whole curve — drive the tank harder (within compression limits).
- Loaded Q: the f0/2QL term sets the corner where the 1/f² skirt begins. High-Q resonators (SAW, BAW, crystal, dielectric) push that corner in close and slash the skirt — a crystal's Q of ~100,000 is why a crystal oscillator buries an LC VCO by 40–60 dB close to carrier.
- Flicker corner fc: device 1/f noise (worst in CMOS, better in SiGe/bipolar) adds the innermost 1/f³ region.
Design lever: doubling loaded Q drops the 1/f² skirt by 6 dB. This is why PLL designers obsess over tank Q and why dielectric-resonator oscillators exist despite their size.
If you are designing the oscillator itself, the companion piece on VCO design digs into how tank topology and varactor choice trade tuning range against the very Q that Leeson punishes you for losing. For the loop filter and divider-noise side of the story, see our note on PLL loop filter design.
Impact on ADCs: the jitter-limited SNR wall
For a sampling ADC, clock jitter translates directly into voltage error, and the error grows with input frequency because a fast-slewing signal moves further during a given timing slip. The aperture-jitter-limited SNR is:
SNRjitter = −20·log10( 2π · fin · σt )
The brutal takeaway: this limit depends only on the input frequency and the jitter, not on the number of bits. Consider a scenario you will meet in any RF-sampling design review:
| Input fin | RMS jitter σt | Jitter-limited SNR | Effective bits (ENOB) |
|---|---|---|---|
| 10 MHz | 1 ps | 84 dB | ~13.6 |
| 100 MHz | 1 ps | 64 dB | ~10.3 |
| 1 GHz | 1 ps | 44 dB | ~7.0 |
| 1 GHz | 100 fs | 64 dB | ~10.3 |
A pristine 16-bit converter clocked by a 1 ps jitter source collapses to about 7 effective bits at a 1 GHz input — you paid for 16 bits and threw away nine. That is why direct-RF-sampling data converters demand sub-100-fs clock sources, and why datasheet SNR curves roll off with fin. When you simulate the full chain in Cadence Spectre or verify the sampling front end, the clock's integrated jitter is the number you feed in, not a vague "phase noise is fine."
Impact on SerDes: eye closure and BER
In a high-speed serial link — PCIe, 112G Ethernet, a DDR interface — jitter eats directly into the timing margin of the data eye. The receiver must sample inside a shrinking horizontal opening, and jitter is decomposed for budgeting into random jitter (RJ, unbounded Gaussian, specified as an RMS value) and deterministic jitter (DJ, bounded: ISI, duty-cycle distortion, crosstalk, periodic jitter from supply or reference spurs).
Total jitter at a target bit-error rate is combined as TJ = DJ + n·RJ, where n comes from the BER (n ≈ 14.07 for 1e-12, 14.69 for 1e-15). A 32 Gb/s lane has a unit interval of just 31.25 ps; if DJ is 8 ps and RJ is 0.5 ps RMS, TJ at 1e-12 is roughly 8 + 14.07·0.5 ≈ 15 ps — nearly half the UI gone before the channel and equalizer even get a vote. Reference-clock phase noise (especially spurs that become periodic jitter) propagates through the CDR; a spur inside the CDR loop bandwidth is tracked out, one just above it is not, which is why SerDes clock budgets care about the shape of L(f), not a single integrated number. Tools such as Siemens HyperLynx and Keysight ADS model this eye closure with statistical jitter decomposition before silicon exists.
Where domains meet: an ADC cares about jitter integrated over a wide band (one scalar σt); a SerDes CDR cares about the frequency profile of L(f) relative to its loop bandwidth. Same oscillator, two different questions.
Measuring and budgeting in practice
On the bench you measure L(f) with a phase-noise analyzer (cross-correlation instruments like the Rohde & Schwarz FSWP, or source-source setups) and let it integrate to jitter over your band. In simulation, use Pnoise/HBnoise in Cadence Spectre RF or harmonic-balance noise in Keysight ADS for the oscillator, then hand the integrated jitter to the ADC or SerDes system model. Always agree the integration band up front — "2 ps jitter" is meaningless without "from 12 kHz to 20 MHz." For hands-on labs on measuring oscillator purity and running these RF noise simulations, the training track at ChipXpert's VLSI training pairs well with the theory here.
FAQ
Are phase noise and jitter the same thing?
They describe the same physical phase perturbation in different domains. Phase noise is the frequency-domain spectral density L(f) in dBc/Hz; jitter is the time-domain timing error in seconds. You convert from L(f) to RMS jitter by integrating the linear spectral density over a band and scaling by 1/(2πf0).
Why does ADC SNR depend on input frequency and not resolution?
Jitter error is the clock timing slip multiplied by the signal's slew rate. A higher input frequency slews faster, so the same timing error produces a larger voltage error. The resulting SNR floor, SNR = −20·log10(2π·fin·σt), contains no bit count — it caps every converter regardless of resolution.
How do I lower an oscillator's phase noise?
The Leeson model gives the levers: raise the loaded Q of the resonator, increase the signal power in the tank, and choose a device technology with a low flicker (1/f) corner. Dividing the frequency down also helps (20·log10(N) improvement), while multiplying up hurts by the same factor.
What is the difference between random and deterministic jitter?
Random jitter is unbounded, Gaussian, and dominated by thermal and flicker noise; it is specified as an RMS value and scaled by a BER-dependent factor. Deterministic jitter is bounded and has identifiable causes — inter-symbol interference, duty-cycle distortion, crosstalk, and periodic jitter from spurs — so it is specified peak-to-peak.
Want to design clean clocks and read phase-noise plots like a pro? The CourseTron Analog & Mixed-Signal track walks you from the Leeson model to full ADC/SerDes jitter budgeting with real Cadence and Keysight labs.