In short: A VCO converts a tuning voltage into a frequency; ring oscillators give you wide tuning range and tiny area but poor phase noise, while LC oscillators give you excellent phase noise at the cost of a bulky inductor and narrow range — and in a PLL the VCO gain KVCO is the knob that trades tuning range against noise and loop stability.
The voltage-controlled oscillator (VCO) is the heart of almost every phase-locked loop (PLL), clock generator and RF transceiver you will ever design. It takes a DC control voltage and produces a periodic output whose frequency depends on that voltage. Everything downstream — the jitter on your serial link, the spectral purity of your LO, the reference spur on your frequency synthesizer — traces back to how the VCO was architected. This article walks through the two dominant topologies, the parameters interviewers actually ask about (KVCO, phase noise, tuning range), and how they couple inside a loop.
What a VCO actually does
Ideally the output frequency is a straight line in the control voltage: fout = f0 + KVCO·Vctrl. The slope KVCO (in Hz/V, or rad/s/V when you work in the loop's phase domain) is the VCO gain. A 2.4 GHz LC-VCO that sweeps from 2.3 to 2.5 GHz as Vctrl moves 0.2 V to 1.0 V has KVCO = 200 MHz / 0.8 V = 250 MHz/V. Keep that number in your head — it reappears in the loop bandwidth, the spur levels and the lock range.
Ring oscillators: wide range, small area
A ring oscillator is simply an odd number of inverting stages connected in a loop (or an even number of differential stages with one crossover). The signal chases its own tail: with N stages each contributing delay td, the oscillation period is 2·N·td, so fosc = 1/(2·N·td). You tune it by starving the stages of current (a current-starved inverter), varying the load, or shifting the supply — anything that changes td.
The appeal is obvious for a digital designer: no inductor, so the layout is a few microns of standard cells, it ports trivially across process nodes, and the tuning range can exceed an octave (2:1 or more). That is why ring VCOs dominate inside CPU/SoC clock PLLs and clock-and-data-recovery (CDR) circuits synthesized with Synopsys Design Compiler and placed with Cadence Innovus.
The price is phase noise. Because a ring stores energy only in parasitic capacitance, it has no high-Q filtering; every stage's thermal and flicker noise modulates the delay directly. Ring VCOs typically sit 20–30 dB worse in phase noise than an LC VCO at the same offset and frequency.
LC oscillators: clean spectrum, bulky inductor
An LC VCO builds a resonant tank from an on-chip spiral inductor L and a varactor Cvar, with a cross-coupled transistor pair supplying the negative resistance that cancels tank loss and sustains oscillation. The frequency is set by resonance: f0 = 1/(2π√(L·C)). You tune by changing the varactor capacitance with Vctrl, and usually add a switched-capacitor bank for coarse bands.
The tank's quality factor Q is what buys the clean spectrum — Leeson's model shows phase noise scales as 1/Q². A respectable integrated tank reaches Q of 10–15, enough to hit −120 dBc/Hz at a 1 MHz offset from a 5 GHz carrier. That is why every cellular, Wi-Fi and SerDes PLL that cares about EVM or BER uses an LC VCO, verified in Cadence Spectre RF (pnoise analysis) or Keysight ADS.
Phase noise: the figure of merit that matters
Phase noise L(Δf) describes how power leaks into sidebands offset Δf from the carrier, in dBc/Hz. Leeson's equation captures the three regions you see on a log-log plot: a 1/f³ flicker-dominated close-in slope, a 1/f² region set by thermal noise and tank Q, and a flat noise floor far out. The single-sideband form is:
L(Δf) = 10·log[ (2FkT/Psig) · (1 + (f0/2QΔf)²) · (1 + Δf1/f³/Δf) ]
Tuning range vs. KVCO: the designer's tension
You might think "just crank KVCO for wide range." But KVCO is also a gain that multiplies every noise and ripple on the control line. A noisy charge pump or leaky loop filter injects Vctrl ripple; that ripple becomes FM modulation of magnitude KVCO·Vripple, directly raising reference spurs and close-in noise. A large KVCO also stiffens loop dynamics and can push the PLL toward instability.
The standard fix is a switched-capacitor bank: split the tuning into coarse digital bands (choosing one keeps KVCO low per band) plus a fine analog varactor for the loop to pull. This is how you get a 20% total tuning range while keeping KVCO down to a few tens of MHz/V inside any one band.
| Attribute | Ring VCO | LC VCO |
|---|---|---|
| Phase noise @1 MHz | −85 to −100 dBc/Hz | −115 to −125 dBc/Hz |
| Tuning range | Very wide (>50%, often octave) | Narrow (10–25%) |
| Area | Tiny (no inductor) | Large (spiral inductor) |
| Power | Low–moderate | Moderate–high |
| Typical use | SoC clocking, CDR | RF LO, SerDes, cellular |
Rule of thumb: pick a ring VCO when range and area dominate (digital clocking); pick an LC VCO when spectral purity dominates (anything radio or high-speed serial). A good interview answer always names the application before the topology.
How the VCO lives inside the PLL
In a charge-pump PLL the VCO is the integrator of the loop: its phase is the integral of frequency, so it contributes a pole at the origin. The open-loop gain combines the phase-detector/charge-pump gain, the loop filter and KVCO; the loop bandwidth and phase margin depend directly on KVCO. The divider ratio N divides KVCO in the loop, which is why high-N synthesizers are so sensitive to VCO gain. If you have not yet mapped out that loop, start with our primer on PLL design basics, then come back here and study how VCO gain sets bandwidth. For the companion topic of how loop filters shape spurs, see charge-pump and loop-filter design.
For anyone moving from coursework to tape-out-grade schematics, hands-on tool experience matters: companies like Avecas design services run production RFIC VCO blocks in Cadence Virtuoso and Spectre, and that is the exact flow we mirror in our labs.
Ready to design a VCO from tank to tape-out? Our CourseTron Analog & RF IC course takes you through ring and LC VCOs, Spectre RF phase-noise setup and full PLL integration with real foundry PDKs.
Frequently asked questions
Why does a ring VCO have worse phase noise than an LC VCO?
A ring stores energy only in parasitic capacitance and has no resonant, high-Q filtering, so transistor thermal and flicker noise modulate the stage delay directly. An LC tank with Q of 10–15 filters that noise, and Leeson's model shows phase noise improves as 1/Q², giving the LC VCO a 20–30 dB advantage at the same offset.
What is a good value for KVCO?
There is no universal number — it depends on your required tuning range and loop bandwidth. The design goal is to keep KVCO as low as the range allows (often tens of MHz/V per band) because it multiplies control-line ripple into spurs. Wide total range is achieved with switched-capacitor banks rather than a single high KVCO.
How do I simulate VCO phase noise?
Use a periodic steady-state (PSS) analysis to find the oscillation point, then a pnoise analysis in Cadence Spectre RF (or harmonic balance in Keysight ADS). Siemens Analog FastSPICE (AFS) is used for larger mixed-signal blocks. Always report L(Δf) at standard offsets like 100 kHz and 1 MHz.
Can a single VCO cover a very wide frequency band?
Not purely with analog tuning — a huge KVCO would wreck the noise and spur budget. Modern designs combine a coarse switched-capacitor array (digital band selection) with a fine varactor, so each band keeps a low KVCO while the banks together span 20% or more.