In short: A series voltage regulator uses an op-amp as an error amplifier that compares a scaled fraction of the output against a fixed reference, then drives a series pass transistor so the output settles at VOUT = VREF(1 + R1/R2).
The linear series regulator is the workhorse that sits behind nearly every clean analog supply rail, and understanding it from the op-amp feedback loop up is one of the most interview-relevant skills an analog designer can own. In this article we build one from scratch, derive the output relationship rigorously, and connect the hand analysis to what you would actually see in a Cadence Virtuoso or LTspice simulation.
The three building blocks
Every op-amp series regulator is assembled from exactly three functional pieces, and once you see them individually the topology stops looking like a cloud of components:
- A voltage reference — a bandgap or Zener-derived node that produces a stable
VREF(commonly 1.205 V for a bandgap) that is as independent of temperature and input voltage as possible. - An error amplifier — the op-amp, which amplifies the difference between the reference and a sampled fraction of the output.
- A series pass element — an NPN/NMOS (or PNP/PMOS for low-dropout variants) transistor in series with the load whose conductance the error amplifier modulates.
Deriving the output relationship
Connect VREF to the op-amp's non-inverting (+) input. Build a resistive divider R1 (top) and R2 (bottom) from the output node to ground, and feed the divider tap into the inverting (−) input. The pass transistor's base/gate is driven by the op-amp output; its collector/drain connects to the raw input VIN and its emitter/source becomes VOUT.
The regulation mechanism is pure negative feedback. The op-amp forces its two inputs to be equal (the virtual-short condition), so the voltage at the divider tap must equal the reference:
VTAP = VREF
The divider sets VTAP = VOUT · R2/(R1 + R2). Setting the two equal and solving:
VOUT = VREF · (R1 + R2)/R2 = VREF(1 + R1/R2)
With a 1.205 V bandgap reference, R1 = 3.3 kΩ and R2 = 1 kΩ you get VOUT = 1.205 × (1 + 3.3) = 5.18 V. Trim R1 to 3.15 kΩ and you land on a clean 5.0 V.
Why the feedback loop actually regulates
Suppose the load suddenly draws more current and VOUT sags. The tap voltage falls below VREF, so the op-amp sees a positive differential input and drives its output harder. That increases the pass transistor's base drive, lowering its collector-emitter voltage drop and restoring VOUT. The correction happens continuously — the loop never "switches," which is precisely why linear regulators are quiet enough for RF front-ends, ADC references, and sensitive analog chains.
Loop gain is what sets regulation quality. If the open-loop error amplifier gain is 80 dB (×10,000) and the feedback factor β = R2/(R1+R2) = 0.233, the loop gain T ≈ 2,330. A 1 V change in VIN then produces only about 1/2330 ≈ 0.4 mV of output change — that is your line regulation.
Headroom, dropout, and choosing the pass device
The pass transistor must stay in its active (saturation, for a MOSFET) region. For a classic NPN emitter-follower pass stage, VIN must exceed VOUT by at least VBE plus the op-amp's output swing headroom — typically 1.5–2 V. If you need a smaller difference, you move to a low-dropout (LDO) topology using a PMOS/PNP pass device, where dropout can fall below 200 mV. The trade-off is loop stability: the common-source PMOS adds a high-impedance pole at the output, so LDOs demand careful compensation and often an explicit output-capacitor ESR window.
| Parameter | Standard NPN series | PMOS LDO |
|---|---|---|
| Dropout voltage | 1.5–2 V | 0.1–0.3 V |
| Pass device drive | Current into base | Voltage on gate |
| Dominant output pole | Low-impedance emitter | High-impedance drain |
| Stability | Easy | Needs ESR/comp care |
Watching the loop settle (animation)
Practical pitfalls and simulation tips
- Divider current vs. accuracy: too little bleed current through R1/R2 lets op-amp input bias current corrupt the tap voltage; too much wastes quiescent power. A few tens of microamps is a common compromise.
- Startup and foldback: add current limiting (a sense resistor plus a clamp transistor) so a shorted output does not vaporize the pass device.
- Stability in SPICE: run an AC analysis with the loop broken (the classic Middlebrook injection) in LTspice or Cadence Spectre to measure phase margin — aim for 45–60°. Siemens' AFS and Cadence Spectre both handle the stb loop-gain analysis directly.
For a deeper treatment of the pass element itself, see our companion piece on the series pass voltage regulator, and if you want to contrast this against switching topologies read buck converter control loops. Teams building production silicon around these cells often partner with a dedicated analog house such as Avecas analog design services for the layout and verification phase.
Want to design, simulate, and tape out regulators like this with hands-on Virtuoso and Spectre labs? Explore the CourseTron Analog Design track and start building real supplies from the feedback equation up.
Frequently asked questions
Why connect the reference to the + input and the divider to the − input?
Negative feedback requires that a rise in output pushes the loop to reduce drive. Sensing the output through the divider on the inverting input achieves exactly that; swapping them would make the loop positive-feedback and latch to a rail.
Can I set V_OUT below V_REF?
Not with this simple divider — the formula VOUT = VREF(1 + R1/R2) is always ≥ VREF. For sub-reference outputs you need a reference divider or a different feedback injection scheme.
What limits the line and load regulation?
Both are set by loop gain. Higher error-amplifier gain and a well-chosen pass device give tighter regulation; the reference's own temperature coefficient then becomes the floor on accuracy.
Why do LDOs need a specific output capacitor?
The PMOS pass device places the dominant pole at the high-impedance output. The capacitor's ESR adds a compensating zero; too little or too much ESR moves that zero out of the stable window and the loop rings or oscillates.