In short: A series-pass voltage regulator places a transistor between the raw supply and the load, and a negative-feedback loop (reference + error amplifier) continuously adjusts that transistor's drop so the output stays fixed even as input and load current wander.
Nearly every analog or mixed-signal chip you will ever bring up depends on a clean, stable rail. The series-pass regulator — the architecture behind every classic three-terminal regulator and every modern low-dropout (LDO) — is how that rail is held steady. Understanding it cold is worth real interview points, because it is the simplest complete example of a closed analog feedback loop doing useful work.
The core idea: a controlled resistor in series
Imagine the pass transistor as a variable resistor sitting in series between the unregulated input VIN and the load. If the output VOUT starts to sag, the loop lowers the transistor's effective resistance so more voltage reaches the load. If VOUT rises, the loop increases the drop. The pass device absorbs the difference (VIN − VOUT) as heat, which is why linear regulators are inefficient but electrically quiet.
Efficiency of a linear series regulator is approximately VOUT/VIN. Dropping 12 V to 5 V at 1 A dissipates 7 W in the pass device and wastes ~58% of the input power — the whole reason switching converters exist.
The four building blocks
- Pass device (Q1): an NPN/PNP BJT or a power MOSFET that carries the full load current. In an NPN-follower topology VOUT = VB − VBE; a PMOS or PNP pass device gives much lower dropout — the defining feature of an LDO.
- Voltage reference: a bandgap (≈1.205 V) prized for its low temperature coefficient, often trimmed to a few tens of ppm/°C.
- Feedback divider (R1, R2): scales VOUT down to the reference level, setting the regulated value: VOUT = VREF(1 + R1/R2).
- Error amplifier: a high-gain op-amp that drives the error between the divided feedback and VREF toward zero.
How the negative feedback actually regulates
Suppose VOUT is 5.00 V with VREF = 1.25 V and R1/R2 chosen for a gain of 4. The divider feeds 1.25 V back. Now a sudden load step pulls VOUT down to 4.90 V. The feedback node drops to ~1.225 V, the error amp sees a positive error at its non-inverting input, and it increases drive to the pass device — lowering its drop and pushing VOUT back up. The loop settles when the fed-back voltage again equals VREF. Because the amplifier gain is large (often 60–80 dB), the residual error is tiny.
The DC accuracy improves by the loop gain. With 1000× (60 dB) loop gain, a 10% change in input or load changes VOUT by only ~0.01% — this is why load and line regulation specs on a good LDO are in the millivolt range.
Dropout, headroom and the LDO distinction
The dropout voltage is the minimum VIN − VOUT at which regulation still holds. A classic NPN Darlington pass stage (like the 7805) needs ~2 V of headroom. Replacing it with a PMOS pass device whose drop is just ILOAD×RDS(on) gives dropout of 100–300 mV — essential for battery systems where VIN sags toward VOUT. This single change is the entire reason the LDO family exists.
| Topology | Pass device | Typical dropout | Use case |
|---|---|---|---|
| Standard linear (7805) | NPN / Darlington | ~2 V | Mains-derived rails with headroom |
| LDO | PMOS / PNP | 0.1–0.3 V | Battery, point-of-load |
| Discrete lab regulator | Power BJT + op-amp | 1–3 V | Teaching, bench supplies |
Stability: the catch nobody mentions until it oscillates
Because the loop contains a high-gain amplifier and the pass device, the regulator is only as good as its phase margin. The output capacitor and its equivalent series resistance (ESR) place a zero that many older LDOs rely on for stability — swap in a modern low-ESR ceramic and a poorly compensated LDO will ring or oscillate. In a real IC design flow you would close this loop in a SPICE simulator — Cadence Spectre or Synopsys HSPICE — run an AC stability (STB) analysis, and confirm 45–60° of phase margin across load and temperature corners before committing to silicon.
For teams building the regulator inside a chip, the pass FET, bandgap and error amp are all laid out and verified with tools like Siemens Calibre for DRC/LVS and Cadence Virtuoso for the analog schematic and layout. This is exactly the kind of block covered in hands-on custom analog IC design services work.
Series vs. shunt — pick the right regulator
The series-pass device dominates when efficiency and moderate current matter. Its sibling, the shunt voltage regulator, instead diverts excess current to ground and shines for very low, fixed loads or as a simple reference. If you need to understand how the reference at the heart of both is built, study the bandgap voltage reference next — it is the quiet workhorse of every precision analog rail.
Want to design, simulate and tape out your own LDO? The analog track in our CourseTron course catalog walks you from feedback theory to a stability-verified layout.
Frequently Asked Questions
Why is a series-pass regulator inefficient?
The pass transistor drops the difference between input and output while carrying the full load current, so it dissipates (VIN − VOUT)×ILOAD as heat. Efficiency can never exceed VOUT/VIN.
What sets the output voltage?
The reference and the feedback divider: VOUT = VREF(1 + R1/R2). The error amplifier forces the divided feedback to equal VREF, so changing R1/R2 reprograms the rail.
What makes an LDO different from an ordinary linear regulator?
The LDO uses a PMOS or PNP pass device whose drop is just I×RDS(on), giving a dropout of a few hundred millivolts instead of ~2 V — critical when the input is only slightly above the output.
Why does my LDO oscillate with a ceramic output capacitor?
Older LDOs depend on the output capacitor's ESR to create a compensating zero. Low-ESR ceramics remove that zero and erode phase margin, causing ringing or oscillation. Use a capacitor in the datasheet's stable ESR window, or a ceramic-stable LDO.