MOSFET Threshold Voltage

In short: Threshold voltage (Vt) is the gate-to-source voltage at which a MOSFET's surface inverts and a conducting channel forms; it rises with substrate doping and oxide thickness, shifts with body bias through the body effect, and is extracted from measured or simulated Id-Vgs curves using linear extrapolation or a constant-current criterion.

What threshold voltage actually means

A MOSFET does not switch on at a magic voltage. As Vgs rises, the surface of the p-type body first accumulates holes, then depletes, and finally fills with electrons. The conventional definition of Vt is the gate voltage at which the surface potential equals twice the Fermi potential, ψs = 2φF, so the electron concentration at the surface equals the hole concentration deep in the bulk. At that point strong inversion begins and drain current rises sharply.

The textbook expression for an NMOS is:

Vt = VFB + 2φF + sqrt(2·q·εSi·NA·(2φF + VSB)) / Cox
φF = (kT/q)·ln(NA/ni)    Cox = εox / tox

Each term has a physical job. VFB (flat-band voltage) cancels the work-function difference between gate and silicon plus any oxide charge. 2φF bends the bands enough to invert the surface. The square-root term is the gate voltage needed to support the fixed depletion charge under the channel, divided by the oxide capacitance that couples gate to silicon.

Dependence on doping

Substrate doping enters twice. It raises φF logarithmically, and it raises depletion charge as the square root of NA. For NA = 10¹⁷ cm^-3 at 300 K with ni ≈ 10¹⁰ cm^-3, φF = 0.0259 × ln(10⁷) ≈ 0.42 V, so 2φF ≈ 0.84 V. Quadrupling NA roughly doubles the depletion term, which is why Vt shifts by hundreds of millivolts across process options.

In practice foundries do not change the whole substrate; they tune Vt with a channel implant, typically boron for NMOS. A shallow implant adds charge near the surface and shifts Vt almost linearly with dose. This is how a single process offers HVT, SVT, LVT and ULVT flavours, which synthesis and place-and-route tools in Synopsys Fusion Compiler or Cadence Genus and Innovus then mix to trade leakage against speed.

Key fact: Subthreshold leakage scales as exp(−Vt / (n·kT/q)). With a slope of about 80 mV/decade, lowering Vt by 80 mV raises off-current roughly tenfold, which is why multi-Vt libraries exist.

Dependence on oxide thickness

The depletion term is divided by Cox, so a thinner oxide reduces its weight. Define the body-effect coefficient γ = sqrt(2·q·εSi·NA) / Cox. For NA = 10¹⁷ cm^-3:

Thick-oxide devices therefore sit at higher Vt for the same doping, and they are far more sensitive to body bias. Modern high-k metal-gate stacks keep a thin equivalent oxide thickness (EOT) while using the gate metal's work function, rather than heavy channel doping, to set Vt. That reduces random dopant fluctuation, a major source of Vt mismatch in analog pairs.

Body bias and the body effect

When the source is raised above the body (VSB > 0), the depletion region widens and needs more gate voltage to invert the surface. Vt becomes:

Vt = Vt0 + γ·( sqrt(2φF + VSB) − sqrt(2φF) )

Using the 2 nm device above (γ ≈ 0.11, 2φF = 0.84 V) with VSB = 0.5 V gives ΔVt ≈ 0.11 × (1.155 − 0.917) ≈ 26 mV. The 10 nm device gives about 0.53 × 0.24 ≈ 127 mV. This matters in stacked structures such as source followers, cascodes and NAND stacks, where upper transistors have their source above the body. For a deeper treatment see our guide to the body effect in MOSFET.

Designers also use it deliberately. Forward body bias lowers Vt for speed, reverse body bias raises it to cut standby leakage, and FD-SOI processes expose this as a back-gate knob with far stronger control than bulk CMOS.

Key fact: The body effect is not a defect of the device; it is the gate-to-body capacitor divider. The effective transconductance from the body, gmb, equals roughly gm·γ / (2·sqrt(2φF + VSB)), typically 0.1 to 0.3 of gm.

How to extract Vt

No measurement sees "the" threshold directly, so every extraction method is a convention. The right one depends on what you want to compare.

• Linear extrapolation (gm,max): Bias Vds at 50 to 100 mV, sweep Vgs, find the point of maximum gm, draw the tangent to Id-Vgs there, and read its Vgs-axis intercept. Then Vt = Vgs,int − Vds/2. It is the classic approach but depends on source/drain series resistance and mobility degradation.
• Constant current: Define Vt as the Vgs where Id = I0 × (W/L), commonly I0 = 100 nA. It is simple, robust, and the usual choice in foundry PDK reports and model-card checks, but the value depends on the chosen I0.
• Second-derivative: Find the peak of d²Id/dVgs². It highlights the weak-to-strong inversion transition, though differentiation amplifies noise.
• Y-function: Y = Id / sqrt(gm) is linear in Vgs above threshold, and largely immune to series resistance. Extrapolating Y to zero gives Vt cleanly.

In simulation, the same sweeps run in Cadence Spectre, Synopsys HSPICE or Siemens Eldo, and the calculator functions in Virtuoso ADE or Custom WaveView post-process the result. For BSIM models, remember the model's own VTH0 parameter is a long-channel, zero-bias value; the simulator's reported vth operating-point value includes short-channel, DIBL and body effects.

Key fact: Quote Vt together with its method, Vds, W/L and temperature. Vt typically falls by 1 to 2 mV per kelvin as temperature rises, so a "0.45 V" device may sit near 0.40 V at 125 °C.

Short-channel and analog design implications

In short-channel devices the drain's electric field lowers the source barrier (DIBL), so Vt falls as Vds rises; reading Vt at Vds = 50 mV versus Vds = VDD can differ by 50 to 100 mV in a 28 nm node. Vt also rolls off with decreasing L because the gate shares control of the depletion charge with the source and drain junctions. Layout adds more: well proximity effect and STI stress can move Vt of identical transistors by tens of millivolts, which is why analog designers keep matched devices in common-centroid layouts. A pair of devices with 10 mV of Vt mismatch drives that same 10 mV of input offset, so Vt control is an analog accuracy issue, not just a leakage one. To dig into biasing consequences, read our walkthrough on the MOSFET small-signal model.

Teams that need device characterisation or PDK-level Vt validation can engage Avecas design services for silicon-proven analog and mixed-signal support.

Frequently asked questions

Why is 2φF the inversion condition?

At ψs = 2φF the surface electron density equals the bulk hole density NA. Beyond that, each extra millivolt of gate voltage mostly adds inversion charge instead of bending the bands further, because the electron density grows exponentially with ψs.

Does PMOS have a negative Vt?

Yes. For an enhancement PMOS, Vt is negative in the usual convention, and body bias and doping act symmetrically with polarities reversed. Designers often quote |Vt|.

Which extraction method should I use for model validation?

Use constant current for quick PDK comparisons, and gm,max or Y-function when you need a physical, bias-independent threshold. Always report the method alongside the number.

Why does simulated Vt differ from the datasheet value?

Datasheets usually cite a constant-current Vt at a specific Vds, W/L and temperature. Simulators report an operating-point vth that includes body effect, DIBL and short-channel roll-off at the actual bias.