Analog

Body Effect in MOSFET

By CourseTron Team ·  7 min read ·  Updated Oct 2026 💬 𝕏 in f
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    In short: When the source sits above the body (VSB > 0), the channel's depletion region widens and needs more gate voltage to invert, so VT rises by γ(√(2φF + VSB) − √(2φF)).

    Why the body is a second gate

    Most textbook MOSFET equations quietly assume the source and the substrate are tied together. In a discrete NMOS that is easy: you short the pins. In an integrated circuit it often cannot be done. All NMOS devices of a bulk CMOS die share one p-type substrate, tied to ground, yet the source of a transistor stacked above another in a NAND gate or a cascode sits well above ground. That gap between source and bulk is VSB, and it changes the threshold voltage. This is the body effect, also called the back-gate effect.

    The intuition is electrostatic. The gate must supply enough charge to do two jobs: uncover fixed acceptor ions in the depletion region and then pull mobile electrons into the inversion layer. Reverse-biasing the source-body junction drags the depletion region deeper, so there are more fixed ions to uncover before any electron can accumulate. The gate pays that extra charge as extra voltage. If you want the baseline definition first, read our primer on MOSFET threshold voltage.

    The equation and what each term means

    For an NMOS device the threshold is:

    VT = VT0 + gamma * ( sqrt(2*phiF + VSB) - sqrt(2*phiF) )

gamma = sqrt(2*q*eps_Si*NA) / Cox
phiF  = (kT/q) * ln(NA / ni)
    • VT0 is the zero-bias threshold (VSB = 0).
    • φF is the Fermi potential of the substrate. With NA = 1017 cm-3 at 300 K it is about 0.41 V, so 2φF is roughly 0.8 V.
    • γ (units V1/2) is the body-effect coefficient. It grows with doping and shrinks with oxide capacitance, so thin oxides and light doping give a small γ.
    • VSB is source-to-body voltage, always taken positive for NMOS in normal operation. For PMOS the signs flip and VBS (body above source) raises |VT|.

    Key fact: the shift goes with the square root of (2φF + VSB), so the first volt of source lift hurts the most and later volts add progressively less.

    Depletion region before and after source-body bias A) VSB = 0 V Gate n+ S n+ D depletion: thin p-substrate (bulk = 0 V) B) VSB = 2 V Gate n+ S n+ D depletion: deeper, more ions p-substrate (bulk = 0 V) Deeper depletion = more fixed charge to uncover = higher VT CourseTron · coursetron.com
    Raising the source above the bulk reverse-biases the source-body junction and widens the depletion layer under the channel.

    A worked example with real numbers

    Take a 0.18 µm-class NMOS with VT0 = 0.45 V, γ = 0.4 V1/2 and 2φF = 0.8 V. The base term is √0.8 = 0.894.

    VSB√(0.8 + VSB)ΔVTVT
    0 V0.8940 mV0.45 V
    0.5 V1.14098 mV0.55 V
    1.0 V1.342179 mV0.63 V
    2.0 V1.673312 mV0.76 V
    3.0 V1.949422 mV0.87 V

    With a 1.8 V supply, a source lifted by 1 V loses 180 mV of overdrive on top of the 1 V it already lost to the source rise. That is a big hit to drive current, which scales with (VGS − VT)2 in the long-channel model.

    Threshold shift versus VSB (gamma = 0.4, 2phiF = 0.8 V) 98 mV 179 mV 312 mV 422 mV 0 1 V 2 V 3 V VSB (volts) ΔVT CourseTron · coursetron.com
    The curve is concave: most of the damage arrives in the first volt, which is the square-root behaviour of the equation.

    See it move: depletion breathing with VSB

    Animated: VSB ramps 0 to 2 V and back Gate (VG fixed) p-substrate dark dots = uncovered acceptor ions the gate must cancel all of them bar = required extra VT CourseTron · coursetron.com
    As VSB rises the depletion layer deepens, more ions are uncovered, and the gate needs a larger voltage to invert the surface.

    Where the body effect bites in real circuits

    • Source followers. The output is the source, so VSB equals the output voltage if the bulk is grounded. Gain, which should be near gm/(gm + gmb), drops to roughly 0.8 to 0.9 and the level shift grows with signal. Putting the device in its own n-well (for PMOS or triple-well NMOS) and tying the well to the source removes it.
    • Stacked logic. The top NMOS in a 4-input NAND sees a source lifted by the devices below, so it has the highest VT and the slowest turn-on. Libraries characterize this per pin, and static timing tools such as Synopsys PrimeTime and Cadence Tempus pick it up through the cell tables.
    • Pass transistors. An NMOS passing a high level stops at VDD − VT(VSB), which is why transmission gates pair an NMOS with a PMOS.
    • Analog cascodes. The upper device's gmb adds a back-gate current term, modifying the output resistance and the small-signal model: Id = gmvgs + gmbvbs, with gmb = η gm and η = γ/(2√(2φF + VSB)), typically 0.1 to 0.3.

    Key fact: gmb/gm = η is the number interviewers love. With γ = 0.4 and VSB = 1 V, η = 0.4/(2 × 1.342) = 0.15, so the back gate has about 15% of the front gate's control.

    Using the body effect on purpose

    Designers do not only fight the effect, they exploit it. Reverse body bias (RBB) raises VT in standby to cut subthreshold leakage, which falls roughly one decade per 80 to 100 mV of VT increase. Forward body bias (FBB) lowers VT to speed up critical blocks. FD-SOI processes make this practical, with wide body-bias ranges managed by on-chip bias generators, while bulk finFET nodes have very small γ because the fin is thin and weakly doped, so adaptive body bias is much less effective there. For a refresher on leakage trade-offs see our article on subthreshold leakage in CMOS.

    Simulating and extracting it

    In SPICE-class simulators (Cadence Spectre, Synopsys HSPICE, Siemens Eldo) the body effect comes from the compact model: BSIM4 uses K1 and K2 parameters, which map to γ in the classic Level-1 form. A quick check is a DC sweep of VSB at fixed VDS while reading the VT from the gm-max or constant-current method. In layout, remember that body connections come from well and substrate taps; a poorly tapped bulk adds resistance, so VSB can shift dynamically with substrate current. Teams building analog blocks, such as those at Avecas design services, usually check bulk connectivity in LVS before any other body-effect concern.

    If you want hands-on practice in a structured path, ChipXpert VLSI training covers device physics through full-custom layout, and our own CourseTron courses walk through the same material with simulation labs.

    Common interview traps

    • Saying the body effect lowers VT. For NMOS with the source above the bulk, it raises VT; only forward body bias lowers it.
    • Forgetting that γ is a process constant but the shift is not linear in VSB.
    • Using the zero-bias gm alone in a source follower and ignoring gmb.
    • Assuming a PMOS in the same p-substrate process escapes: it sits in an n-well and has its own γ, and its well is often tied to VDD while its source drops, causing the same effect with opposite polarity.

    Ready to go deeper? Join the CourseTron analog design course on coursetron.com/courses and practise body-effect sweeps, source followers and cascodes in guided labs.

    Frequently asked questions

    What is the body-effect coefficient gamma?

    Gamma is a process constant equal to √(2qεSiNA)/Cox. It sets how strongly the substrate bias changes the threshold voltage. Typical values run from 0.2 to 0.6 V1/2.

    Does the body effect happen in PMOS?

    Yes. A PMOS with its n-well biased lower than its source sees its |VT| rise by the same square-root law, with signs mirrored.

    How do I eliminate the body effect in a circuit?

    Tie the source to the body, which requires an isolated well such as a PMOS n-well or a triple-well NMOS. The cost is area and well capacitance on the source node.

    Is the body effect always bad?

    No. Adaptive body biasing uses it to trade speed against leakage and to compensate process variation, especially on FD-SOI technologies.

    References & Further Reading

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