MOSFET Switching Characteristics

In short: a power MOSFET switches only as fast as its gate driver can charge the gate capacitances (Qgs, then the Miller charge Qgd), and the switching loss is the voltage-current overlap during those intervals, roughly ½·Vds·Id·(tr+tf)·fsw, so gate charge, not on-resistance alone, sets efficiency at high frequency.

Why switching behaviour decides your efficiency

Pick a MOSFET from its Rds(on) alone and you will be surprised at the first thermal image. A 400 V, 10 A hard-switched stage running at 100 kHz can lose more power in the few nanoseconds of each transition than in the entire conduction interval. A MOSFET is a voltage-controlled device, but the gate is a capacitor, and moving charge in and out of it takes time. That time creates the delays, the slopes and, ultimately, the heat. If you already know the cell and drift-region layout from our power MOSFET structure article, this piece explains how those physical capacitances turn into datasheet numbers.

The three capacitances behind every delay

Datasheets quote Ciss, Coss and Crss, which are really combinations of three internal capacitances:

• Cgs (gate-source): largely fixed, set by gate-oxide and source overlap.
• Cgd (gate-drain, Crss): small but strongly voltage dependent, large when Vds is low and tiny when Vds is high.
• Cds (drain-source): the junction capacitance of the body diode, which with Cgd forms Coss.

Ciss = Cgs + Cgd is what the driver sees before the device conducts. Typical numbers for a 600 V superjunction part: Ciss around 2 nF, Coss around 100 pF, Crss around 5 pF at 100 V. Because Cgd swings from tens of picofarads to several nanofarads as Vds collapses, the gate behaves like a capacitor whose value changes mid-transition. That non-linearity is the origin of the Miller plateau.

Key fact: Crss is tiny on the datasheet, but the Miller effect multiplies it by the voltage gain of the stage, so it dominates the voltage-fall time even though it is the smallest capacitor.

Turn-on, phase by phase

Assume a 10 V driver, a 5 Ω gate resistor Rg, a threshold Vth of 3 V and a clamped inductive load, as in a buck or boost converter.

• Turn-on delay td(on): the driver charges Ciss through Rg. With Ciss = 2 nF and Rg = 5 Ω, τ = 10 ns, and reaching 3 V takes τ·ln(10/7) ≈ 3.6 ns (add internal gate resistance, typically 1 to 3 Ω). Nothing happens at the drain yet.
• Current rise tri: Vgs climbs from Vth toward the plateau voltage, where Id equals the load current (Vplateau ≈ Vth + Id/gm). Vds stays at the full bus voltage because the freewheel diode is still conducting, so power loss builds.
• Voltage fall tfv (Miller plateau): now the diode is off, Vds starts to fall, and Cgd must be discharged by the gate current. Vgs sits flat at the plateau, and all driver current goes into Cgd. The gate current is (10 − 5)/5 Ω = 1 A, so a 10 nC Qgd takes about 10 ns.
• Full enhancement: once Vds has collapsed, Vgs rises on to the driver rail and Rds(on) drops to its datasheet value.

Gate charge: the number worth designing around

Because the capacitances are non-linear, Ciss cannot predict switching time reliably. Gate charge can, since it integrates the real current through the real capacitance. Datasheets plot Vgs against charge delivered at a constant gate current, and the curve has three zones: Qgs (charge to the start of the plateau), Qgd (the plateau itself, the Miller charge) and the overdrive region that follows. Total Qg is what you need for driver power and sizing.

Key fact: Switching time is roughly charge divided by gate current: t ≈ Q / Ig. Halve Rg (or double driver strength) and the transition time halves, at the cost of higher dv/dt and EMI.

Turn-off and the dv/dt trap

Turn-off is the mirror image: td(off) while Vgs falls from the driver rail to the plateau, then trv as Vds rises, then tfi as current collapses. Turn-off is usually the more dangerous edge. The drain current falling through the loop inductance (di/dt times a few nH) overshoots Vds, and a fast rising Vds injects current through Cgd into the gate. If the off-state gate impedance is high, that current lifts Vgs above Vth and the opposite device in a half-bridge turns on, causing shoot-through. Fixes include a low-impedance turn-off path (a diode across Rg or a separate Rg(off)), a negative gate drive for SiC and large devices, and a Cgs-to-Cgd ratio well above 1.

A worked switching-loss budget

Take the device above in a 400 V, 10 A, 100 kHz hard-switched boost stage with tr = 20 ns and tf = 15 ns (including the Miller intervals):

Switching loss exceeds conduction loss, and it scales linearly with frequency. Doubling fsw to 200 kHz adds another 7.8 W. This is why wide-bandgap devices with Qgd of a few nanocoulombs matter, and why the figure of merit Rds(on) × Qgd is a better selector than Rds(on) alone. Soft-switching topologies (ZVS in LLC or phase-shifted bridges) remove the overlap term entirely, leaving mainly gate and conduction loss.

Practical tuning and simulation

• Size Rg from a target dv/dt, not from habit: dv/dt ≈ Ig / Cgd during the plateau. Start near 5 to 10 Ω and tune against measured overshoot.
• Keep the gate loop tiny. Five nH of loop inductance with a 4 A/ns gate edge produces 20 V of ringing, enough to exceed the oxide limit.
• Simulate before layout. Cadence Spectre or Synopsys HSPICE with vendor SPICE models reproduces the plateau, though level-1 models often underestimate Cgd non-linearity. Use a double-pulse test on the bench to verify.
• Do not trust typical values. Qg and td vary with temperature, Vgs and Vds, and datasheet conditions rarely match your design.

Teams building power stages or gate-drive ICs often pair this analysis with layout review; Avecas design services support such analog and mixed-signal work, and ChipXpert training covers the interview-level theory. For the gate-driver side, continue with gate driver design basics.

Want to go from theory to simulation? Explore the analog and power electronics tracks in the CourseTron courses and practise gate-charge calculations on real device models.

Frequently asked questions

What is the Miller plateau and why is Vgs flat there?

While Vds is changing, the entire gate current is consumed charging or discharging Cgd, so there is none left to change Cgs and Vgs holds at roughly Vth + Id/gm. It ends when Vds stops changing.

Why is gate charge better than input capacitance for estimating switching speed?

Ciss is measured at small signal and fixed bias, but Cgd changes by orders of magnitude during a transition. Qg integrates that behaviour, so t ≈ Q/Ig gives a realistic estimate.

Does a faster turn-on always mean lower loss?

It reduces overlap loss, but increases dv/dt, di/dt, ringing and EMI, and can cause false turn-on of the complementary switch. Designers trade loss against stress.

How does gate drive power relate to frequency?

Pgate = Qg × Vdrv × fsw, independent of Rg. Rg only decides where the energy is dissipated, not how much is drawn.