In short: Miller compensation puts a small capacitor across the high-gain second stage of a two-stage op-amp so that the capacitor's effective value is multiplied by the stage gain, pushing the dominant pole far down and the second pole far up (pole splitting) to buy phase margin — at the cost of a right-half-plane zero that you must tame with a nulling resistor.
Almost every two-stage CMOS operational amplifier you will meet in a textbook, a SerDes bias block, or a bandgap buffer relies on Miller compensation for its stability. It is the single most tested analog-design topic in VLSI interviews, and the one candidates most often half-understand. This article walks through why an uncompensated two-stage amp oscillates, how one capacitor fixes it, and the right-half-plane (RHP) zero that comes along for the ride.
Why a two-stage amp needs help
A classic two-stage amp has two high-impedance internal nodes: the output of the differential input stage (node 1) and the output of the common-source second stage (node 2). Each node contributes a pole set by its resistance and capacitance. With comparable pole frequencies, the loop accumulates nearly 180° of phase shift near unity-gain crossover. Close the loop and you have a near-oscillator: phase margin collapses, the step response rings, and the amp may be outright unstable.
Concretely, imagine node 1 at p1 ≈ 2 MHz and node 2 at p2 ≈ 5 MHz with a DC gain of 70 dB. The gain does not fall below unity until well past both poles, so by crossover the phase has already rotated past −180°. We need to separate those two poles dramatically.
The Miller effect, turned into a tool
Bridge node 1 and node 2 with a capacitor Cc across the inverting gain stage (gain −A₂ = −gm2·ro2). Looking into node 1, that capacitor appears as Cc·(1+A₂) — the Miller multiplication. With A₂ of a few hundred, a 1–2 pF physical capacitor behaves like hundreds of picofarads at node 1.
The dominant pole moves to roughly p1 ≈ 1 / (gm2·ro2·ro1·Cc). A larger second-stage gain does not hurt stability here — it helps, because it multiplies Cc harder and drives p1 lower.
Simultaneously, Cc provides a low-impedance path that shunts node 2 at high frequency, so the output pole moves up to p2 ≈ gm2 / CL (with CL the load capacitance). The two poles move apart — hence pole splitting. You can now place the dominant pole so the loop gain falls to unity before the second pole contributes meaningful phase shift, restoring 60°+ of phase margin.
The right-half-plane zero: the catch
The same capacitor creates a feedforward path from node 1 straight to the output. At the frequency where the feedforward current through Cc cancels the gain-path current, there is a transmission zero at z = +gm2/Cc. Because gm2 is positive, the zero sits in the right half-plane.
An RHP zero is nasty: it adds gain like a normal zero but subtracts phase like a pole. If it lands near crossover it can wipe out the phase margin you just earned. In a 180 nm amp with gm2 = 1 mS and Cc = 1.5 pF, the zero sits at about 106 MHz — often uncomfortably close to the unity-gain frequency.
| Element | Before Cc | After Cc |
|---|---|---|
| Dominant pole p1 | ~2 MHz | ~20 kHz (pushed down) |
| Second pole p2 | ~5 MHz | ~80 MHz (pushed up) |
| Phase margin | < 10° (unstable) | 60°+ (stable) |
| New artifact | — | RHP zero at +gm2/Cc |
Killing the RHP zero
- Nulling resistor (Rz): put a resistor in series with Cc. The zero moves to z = 1 / (Cc·(1/gm2 − Rz)). Choosing Rz = 1/gm2 sends the zero to infinity; a larger Rz flips it into the left half-plane, where it can even be used to cancel p2. This is the standard textbook fix.
- Common-gate / voltage buffer: insert a cascode or source follower in the Cc path so current flows one way only, eliminating the feedforward and the zero entirely (indirect / cascode compensation).
- Ahuja (current-buffer) compensation: sense the Cc current through a common-gate device — widely used in low-voltage and LDO designs for better PSRR and power efficiency.
A poly-silicon Rz drifts with temperature while 1/gm2 drifts the other way, so designers often implement Rz as a MOS transistor biased in the triode region to track gm2 and hold the zero cancellation across PVT corners.
Verifying it in the tools
In practice you never trust hand calculations alone. Run an AC analysis (a .ac sweep) in Cadence Spectre or Synopsys HSPICE/PrimeSim, then use a stb (stability) analysis to extract loop gain, phase margin, and gain margin directly. Siemens Eldo/AFS offers the same stability probe. Sweep Cc and Rz across process corners and temperature; watch the RHP zero on the pole-zero (.pz) analysis. A healthy target is 60° phase margin with the second pole at least 2–3× the unity-gain frequency. For hands-on design-service support with such closures, teams often turn to Avecas analog design services.
Stability is only half the story — read our companion piece on phase margin and stability for the frequency-domain picture, and two-stage op-amp design for the full sizing procedure. The full treatment lives in our analog design courses.
Ready to size a compensation network from spec to GDS? Join CourseTron's Analog IC Design track and build a stable two-stage amp in Spectre, hands-on.
Frequently asked questions
Why does Miller compensation improve stability instead of just slowing the amp?
It separates the two internal poles so only one pole dominates the loop below crossover. A single-pole roll-off gives at most 90° of phase shift, guaranteeing margin. The bandwidth reduction is the price of a well-behaved single-pole response.
Is the RHP zero always a problem?
Only if it sits near or below the unity-gain frequency. In low-gm, large-Cc designs the zero can be far out and harmless, but in high-speed amps it routinely threatens margin, so a nulling resistor or current-buffer scheme is standard.
How do I pick the value of Cc?
Start from the unity-gain requirement: Cc ≈ gm1 / (2π·GBW). Then confirm the second pole gm2/CL lands above the crossover with margin to spare, and iterate in simulation across corners.
What is the difference between Miller and cascode (indirect) compensation?
Miller compensation feeds the Cc current back through the gain path, creating the RHP zero. Cascode/indirect compensation routes that current through a low-impedance node, removing the feedforward path and the zero while often giving a higher bandwidth for the same power.