Common-source amplifier

In short: The common source amplifier is the workhorse voltage-gain stage of MOSFET analog design, taking a small signal at the gate and producing an amplified, inverted copy at the drain. Its gain is set by the transconductance g_m and the output resistance, while biasing fixes the operating point and the load and parasitic capacitances shape its frequency response.

What Is a common source amplifier?

A common source amplifier is a single-transistor MOSFET gain stage in which the source terminal is shared (common) between the input and output loops, the gate is the input node, and the drain is the output node. It is the MOS counterpart of the bipolar common-emitter stage and is by far the most-used building block for providing voltage gain in CMOS integrated circuits, from op-amp input stages to RF front-ends.

The idea is simple: a small voltage applied to the gate modulates the channel current. That current flows through a load (a resistor or an active current source) at the drain, and Ohm's law turns the current swing back into a much larger voltage swing. Because an increase in gate voltage pulls the drain down, the stage inverts the signal, giving a negative gain.

Biasing: setting the operating point

Before a transistor can amplify, it must be biased into saturation (the active region), where it behaves as a voltage-controlled current source. The DC operating point defines the quiescent drain current I_D and the gate-source voltage V_GS. For a long-channel MOSFET in saturation:

I_D = ½ · μ_nC_ox · (W/L) · (V_GS − V_TH)²

The quantity (V_GS − V_TH) is called the overdrive voltage, and it is the single most important design knob. A small overdrive gives high gain per unit current but limited swing and speed; a larger overdrive trades gain for headroom and bandwidth.

• Resistive biasing uses a gate divider and a source/drain resistor — simple but sensitive to supply and temperature.
• Current-mirror biasing forces a precise I_D from a reference, making the operating point robust across process and temperature. This is the standard in integrated design.
• A well-chosen bias keeps the drain voltage roughly centred so the output can swing symmetrically without pushing the device into triode.

Small-signal model and gain

To find the gain we replace the DC supplies with ground and model the transistor with its small-signal elements: a dependent current source g_mv_gs between drain and source, and the device output resistance r_o (which captures channel-length modulation, r_o ≈ 1/λI_D). The gate draws no DC current, so the input looks capacitive.

With a drain load R_D, the low-frequency voltage gain is:

A_v = − g_m · (R_D ∥ r_o)

The minus sign is the signal inversion. If the resistor is replaced by an ideal current-source load (an "active load"), R_D → ∞ and the gain collapses to the device's intrinsic gain, A_v = −g_mr_o — the maximum a single transistor can deliver, typically 20–40 dB in modern CMOS.

Frequency response and bandwidth

At low frequencies the gain is flat and set by g_m(R_D∥r_o). As frequency rises, parasitic capacitances begin to short the signal and the gain rolls off. Two capacitances dominate:

• C_gs — gate-to-source, loading the input node.
• C_gd — gate-to-drain, which bridges input and output. Because the output swings in the opposite direction with gain |A_v|, this capacitor appears at the input multiplied by (1 + |A_v|). This amplification of C_gd is the famous Miller effect, and it is usually what limits the bandwidth of a common source amplifier.

The dominant pole sits roughly at f_−3dB ≈ 1 / (2π R_src C_in), where C_in = C_gs + C_gd(1 + g_mR_L). A second pole at the output and a right-half-plane zero (from the feed-forward path through C_gd) appear at higher frequencies. Designers fight the Miller penalty with a cascode stage, which holds the drain of the input device nearly constant and so neutralises C_gd amplification, buying far more bandwidth for the same gain.

Design trade-offs at a glance

• Gain vs. swing: higher load resistance lifts gain but eats output headroom.
• Gain vs. speed: the gain-bandwidth product is roughly fixed for a given device, so chasing gain costs bandwidth.
• Linearity: the square-law relationship makes the stage nonlinear for large signals; small overdrive and feedback (e.g. source degeneration) improve linearity at the cost of gain.

common source amplifier — FAQ

Why does the common source amplifier invert the signal?

Raising the gate voltage increases the drain current. That larger current drops more voltage across the load resistor, pulling the drain node toward ground. So an upward input produces a downward output — a 180° phase inversion, reflected by the minus sign in A_v = −g_m(R_D∥r_o).

What limits the bandwidth of a common source stage?

The Miller effect dominates. The gate-drain capacitance C_gd is effectively multiplied by (1 + |A_v|) at the input, creating a large input capacitance that forms a low-frequency dominant pole with the source resistance. A cascode is the standard remedy.

How do I maximise the gain?

Use an active (current-source) load so the resistance seen at the drain approaches r_o, bias at a small overdrive to raise g_m for a given current, and choose a device with low channel-length modulation for a high r_o. This pushes the gain toward the intrinsic limit g_mr_o.

When should I use a common source amplifier versus a common drain stage?

Use common source when you need voltage gain. Use a common drain (source follower) when you need a low-output-impedance buffer with near-unity gain, for example to drive a resistive or capacitive load without loading the previous gain stage.

Related: op-amp design basics · Glossary · all courses.