In short: A good bias generator produces a reference current that barely moves with supply and temperature — the constant-gm (beta-multiplier) cell pins transconductance to a resistor, PTAT/CTAT combinations cancel temperature drift, and a startup circuit guarantees the whole loop escapes its zero-current state.
Every analog block — an op-amp input pair, an LNA, a comparator, an ADC comparator-preamp — needs a bias current or voltage that stays put. If the tail current wanders 2x across supply and temperature, your amplifier's gain-bandwidth, slew rate, and offset wander with it. Bias circuit design is the quiet discipline that makes the rest of the chip repeatable across a 1.6–3.6 V battery and a −40 to 125 °C automotive range.
Why a resistor-divider bias is not enough
The naive approach — a resistor divider from VDD into a gate — gives a voltage that tracks the supply linearly. A 10% supply ripple becomes a 10% bias shift. Worse, the current it sets depends on the MOSFET's threshold and mobility, both of which swing dramatically over temperature and process corners (slow-slow vs. fast-fast can shift VTH by 100–150 mV in a modern CMOS node). The goal of a real bias network is supply independence and a controlled temperature coefficient, not an accidental one.
Rule of thumb: a self-biased reference's supply sensitivity improves with the loop gain of its feedback. A simple beta-multiplier gets you ~1–5% / V; add a cascode or a regulated supply and you push below 0.1% / V.
The constant-gm (beta-multiplier) core
The workhorse self-biased reference is the constant-gm cell. A PMOS current mirror forces the two branches to carry equal currents. On the NMOS side, one transistor (M1) is sized 1x and the other (M2) is K times wider, with a degeneration resistor RS in M2's source. Setting the two gate-source voltages equal around the loop gives the defining relation:
gm1 = 2 (1 − 1/√K) / RS
The transconductance of M1 is now set only by a resistor and a sizing ratio — not by VDD, and only weakly by process. That is extraordinarily useful: if you build your amplifier's input pair as a scaled copy of M1, its gm (and therefore the GBW when loaded by a fixed capacitor) becomes insensitive to supply. This is why the technique is called constant-gm biasing rather than constant-current biasing.
Startup circuits: escaping the degenerate state
Here is the subtlety that trips up every student in a verification review: the constant-gm loop has two stable operating points. One is the intended current; the other is zero current everywhere, which also satisfies the loop equations. On power-up the circuit can sit in the dead state forever. A startup circuit injects a small current (or pulls a node) to nudge the loop off zero, then switches itself off once the reference is awake so it burns no steady-state power.
A classic implementation is a long-channel MOS "leaker" that senses the bias node and, while that node sits near a rail, dumps a trickle of current into the mirror to kick it alive. In a Cadence Spectre or Synopsys HSPICE deck you must prove startup with a slow VDD ramp (a .tran with a PWL supply) across all corners — a DC operating-point sweep hides the dead state because the solver happily lands on either solution.
If your reference "works in DC but reads 0 µA in transient at the cold-slow corner," suspect a missing or too-weak startup device — not the core. This is one of the most common silicon respins in junior analog designs.
PTAT, CTAT, and shaping temperature behaviour
Two complementary signals let you dial any temperature coefficient you like:
- PTAT (Proportional To Absolute Temperature): the difference of two BJT base-emitter voltages, ΔVBE = (kT/q)·ln(N), rises ~+0.085 mV/°C per decade of current-density ratio. A resistor converts it to a PTAT current.
- CTAT (Complementary To Absolute Temperature): a single VBE falls ~−2 mV/°C.
Sum a PTAT voltage (scaled up ~22x) with one CTAT VBE and the slopes cancel, giving the ~1.25 V bandgap reference that is flat to a few tens of ppm/°C. The same PTAT current is often reused to bias amplifiers, because a PTAT tail current keeps gm of a bipolar pair roughly constant with temperature. Choosing PTAT vs. CTAT vs. zero-TC is a deliberate design knob — see our companion piece on current mirror topologies for how these references fan out to many loads, and bandgap reference design for the curvature-correction details.
Worked numbers
| Target | Approach | Typical result |
|---|---|---|
| gm1 = 200 µS | K = 4, RS = 2(1−0.5)/200µ = 5 kΩ | Set by R only |
| Supply sensitivity | Simple mirror | ~2% / V |
| Supply sensitivity | + cascode mirror | <0.1% / V |
| Reference TC | Bandgap PTAT+CTAT | 20–50 ppm/°C |
Practical pitfalls in layout and verification
- Resistor matters most: since gm is pinned to RS, its absolute tolerance (±15–20% for poly) sets your current spread. Use a trimmable array or accept a wider gm budget.
- Mirror matching: lay out the PMOS pair with common-centroid and dummies; a 1% mismatch directly corrupts the current equality.
- Verify startup at every corner with a transient supply ramp (Spectre/HSPICE), and check the startup device fully disengages so quiescent current meets the µA budget.
- PSRR and noise: cascode the mirror for supply rejection; the reference's 1/f noise shows up on every biased block downstream.
For teams building production references, India-based Avecas analog design services run exactly these corner and startup sign-off flows on commercial SCL and foundry PDKs.
Want to design a constant-gm bias and bandgap from scratch, simulate startup across corners, and tape it out in a PDK? Our hands-on analog track on CourseTron's course catalogue walks you through every schematic and Spectre deck above.
Frequently asked questions
Why does a constant-gm bias improve amplifier bandwidth stability?
Because gain-bandwidth product is gm/(2πCL). If gm is locked to a resistor instead of to VDD or VTH, the amplifier's bandwidth stops drifting with supply and process, which is usually what the system spec cares about.
Is a startup circuit always required?
For any self-biased loop that has a legitimate zero-current solution — yes. Current mirrors driven from an external reference do not need one, but beta-multiplier and bandgap cores do, and omitting it causes intermittent dead-on-boot silicon.
What is the difference between PTAT and CTAT?
PTAT rises with temperature (from ΔVBE), CTAT falls (from a single VBE). Combining them in the right ratio cancels the first-order temperature slope to build a bandgap reference.
How do I prove supply independence in simulation?
Run a DC sweep of VDD and plot the reference current; compute d(IREF)/dVDD as a percentage. Then confirm startup and PSRR with transient and AC analyses across all PVT corners before sign-off.