In short: The 555 is a three-resistor divider that sets 1/3 and 2/3 of the supply as reference levels, two comparators that watch those levels, an SR flip-flop that remembers which side was crossed last, and a discharge transistor plus output stage that act on that memory.
Why the 555 is still worth dissecting
Hans Camenzind designed the 555 at Signetics in 1971, and billions of units later it remains the standard teaching vehicle for mixed-signal thinking. Inside a package that costs a few cents sit a voltage reference ladder, analog comparators, a digital latch and a power output driver. Every one of those ideas reappears in modern SoCs: bandgap-fed comparators in power-management ICs, SR latches in clock-gating cells, open-collector discharge paths in reset supervisors. Interviewers love it because a candidate who can explain the 555 from the transistor level up can usually reason about any analog-to-digital interface block.
This article walks the block diagram from the supply pin to the output pin. If you want to see the chip wired as an oscillator afterwards, continue with the 555 astable multivibrator guide.
The big picture: five blocks, eight pins
The resistor divider: three equal 5 kΩ legs
The name "555" comes from three identical 5 kΩ resistors in series between VCC and ground. They create two taps: 2/3 VCC and 1/3 VCC. At a 9 V supply these are 6 V and 3 V; at 5 V they are 3.33 V and 1.67 V. Because both references are ratiometric, the timing thresholds track the supply, so an RC timing network that charges from the same supply gives an interval that is nearly independent of VCC. That is the single most important design insight in the chip.
The upper tap is brought out as the control voltage pin (5). Driving it with an external source moves the upper threshold, and the lower one follows at half that value. This is how pulse-width modulation and FM tricks work. Leave it unused and you should add a 10 nF capacitor to ground, otherwise supply noise couples directly into the reference.
Key fact: thresholds are 2/3 VCC and 1/3 VCC, so the capacitor swing in astable mode is VCC/3 and the charge time constant ratio gives the famous 0.693 factor (ln 2).
Two comparators: who watches what
The upper comparator compares the THRESHOLD pin (6) against 2/3 VCC. When pin 6 rises above that level its output goes high and resets the latch. The lower comparator compares the TRIGGER pin (2) against 1/3 VCC. When pin 2 falls below that level its output goes high and sets the latch. Note the asymmetry: trigger is level-sensitive and active-low, threshold is active-high.
In the original bipolar design the comparator inputs are transistor bases, so they draw bias current: roughly 0.1 µA at THRESHOLD and 0.5 µA at TRIGGER. The consequence is practical. Threshold current limits the largest usable timing resistor to about 10 MΩ before leakage distorts the period. CMOS versions such as the TLC555 or LMC555 have picoamp inputs, run from about 2 V, and draw tens of microamps instead of milliamps.
The SR flip-flop: the memory that creates hysteresis
A single comparator would chatter around its threshold. The 555 avoids that by using two thresholds and a latch, which is effectively a Schmitt trigger built from discrete blocks. Once the capacitor voltage crosses 2/3 VCC the latch resets and stays reset until the voltage falls below 1/3 VCC, no matter how much noise rides on the signal in between. The hysteresis window is therefore VCC/3 wide.
The RESET pin (4) is an asynchronous, active-low override on the latch, with priority over both comparators. It switches at about 0.7 V, so tie it to VCC when unused. A floating reset pin is one of the most common causes of "my 555 behaves randomly" on a breadboard.
Discharge transistor and output stage
The latch's inverted output drives two loads. The first is an open-collector NPN discharge transistor whose collector is pin 7. When the latch is reset, the NPN saturates and pulls pin 7 to about 0.1 V, dumping the external timing capacitor through a resistor. When the latch is set, the transistor is off and pin 7 floats, so the capacitor charges freely. Because it is a bare collector, pin 7 doubles as a general open-collector output, handy for pulling a bus low.
The second load is the totem-pole output stage on pin 3. The bipolar NE555 can source or sink up to about 200 mA, enough to drive a small relay or LED string directly. Its high level sits roughly 1.7 V below VCC at heavy load (about 3.3 V at 5 V supply, under light load), so it is not a rail-to-rail driver; the CMOS parts are. Remember that sourcing 200 mA through a 1.7 V drop dissipates real heat, so check the package's thermal limits.
Key fact: one-shot pulse width is T = 1.1 × R × C. The capacitor charges from 0 to 2/3 VCC, and ln(3) ≈ 1.0986 gives the 1.1 constant.
Watching the blocks work together
Follow the chip in astable form, capacitor on pins 2 and 6 tied together. The capacitor charges, crosses 1/3 VCC, and nothing happens because the latch is already set. At 2/3 VCC the upper comparator resets the latch, the output falls and the NPN turns on. The capacitor discharges until it crosses 1/3 VCC, the lower comparator sets the latch, and the cycle repeats. The animation below shows that sweep with the two thresholds marked.
Pin function cheat sheet
| Pin | Name | Role |
|---|---|---|
| 1 | GND | Ground return |
| 2 | TRIG | Sets latch when below 1/3 VCC |
| 3 | OUT | Totem-pole output, about 200 mA |
| 4 | RESET | Active-low latch override |
| 5 | CTRL | Access to the 2/3 VCC reference |
| 6 | THR | Resets latch when above 2/3 VCC |
| 7 | DIS | Open-collector capacitor discharge |
| 8 | VCC | 4.5 to 16 V for the bipolar NE555 |
From breadboard to silicon practice
Designers rarely use a 555 inside a modern SoC, but they simulate its structure constantly. In Cadence Spectre or Synopsys HSPICE you can build the whole chip from a resistor ladder, two op-amp comparators and a behavioural latch, then sweep VCC from 4.5 V to 16 V to confirm the period moves less than a few percent. Corner and Monte Carlo runs expose how a 1% mismatch in the 5 kΩ resistors shifts the thresholds. For layout, matching the three resistors with interdigitated or common-centroid placement is exactly the technique taught for any bandgap or DAC ladder. Teams that need custom timing and supervisory blocks in production silicon often engage design-services houses such as Avecas for analog and mixed-signal design. If you want to practise the transistor-level flow, the CMOS comparator design guide covers the same comparator topology in a modern process.
Ready to go beyond one chip? Explore the analog and mixed-signal tracks in our CourseTron courses and build, simulate and layout circuits like this one.
Frequently asked questions
Why is it called the 555?
The name comes from the three 5 kΩ resistors in the internal voltage divider, which set the 1/3 and 2/3 VCC comparator thresholds.
What happens if the control pin is left floating?
It still works because the divider holds the node at 2/3 VCC, but noise can couple in and jitter the timing. A 10 nF capacitor to ground is the standard fix.
Can the 555 run from 3.3 V?
The bipolar NE555 needs about 4.5 V minimum. CMOS versions such as the TLC555 and LMC555 operate down to roughly 2 V and are the right choice for 3.3 V systems.
What does the discharge pin do in a monostable?
It holds the timing capacitor at zero until a trigger arrives, then releases it so the capacitor can charge to 2/3 VCC, which ends the pulse.
References & Further Reading
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