555 Timer Astable Multivibrator

In short: a 555 astable oscillates because its capacitor ramps between 1/3 and 2/3 of Vcc, charging through R1+R2 and discharging through R2 only, which gives f = 1.44 / ((R1 + 2·R2)·C) and a duty cycle of (R1+R2)/(R1+2·R2), always above 50%.

What the 555 is actually doing

The NE555 is a small mixed-signal block: three equal 5 kΩ resistors form a divider from Vcc to ground (hence the name), two comparators, an SR latch, and an open-collector discharge transistor. The divider creates two reference levels, 2/3·Vcc at the upper comparator and 1/3·Vcc at the lower one. In astable mode you wire pin 6 (THRESHOLD) and pin 2 (TRIGGER) together to the timing capacitor, so the same node is watched by both comparators.

When the capacitor voltage rises past 2/3·Vcc, the upper comparator resets the latch: output (pin 3) goes low and the discharge transistor on pin 7 turns on. The capacitor now drains. When it falls below 1/3·Vcc, the lower comparator sets the latch: output goes high and the transistor releases the capacitor, which starts charging again. That hysteresis window, one third of the supply wide, is the whole oscillator. If you have seen a Schmitt trigger with an RC feedback, this is the same idea with the thresholds set by a resistor ladder.

Deriving the timing from the RC equation

An RC node driven toward a final voltage V∞ from a start V0 follows v(t) = V∞ − (V∞ − V0)·e^(−t/τ). Everything in the 555 follows from solving for the time to move between the two thresholds.

Charge (output high). The discharge transistor is off, so the capacitor charges toward Vcc through R1 + R2. It starts at Vcc/3 and must reach 2Vcc/3. The remaining distance to Vcc shrinks from 2Vcc/3 to Vcc/3, a factor of exactly 2, so:

t_high = (R1 + R2) · C · ln 2 ≈ 0.693 · (R1 + R2) · C

Discharge (output low). The transistor now grounds pin 7, so the capacitor decays toward 0 through R2 only. It falls from 2Vcc/3 to Vcc/3, again a factor of 2:

t_low = R2 · C · ln 2 ≈ 0.693 · R2 · C

Add them: T = 0.693·(R1 + 2·R2)·C, so f = 1/T = 1.44 / ((R1 + 2·R2)·C). The duty cycle D = t_high / T = (R1 + R2)/(R1 + 2·R2).

Key fact: the supply voltage cancels out of the frequency. Both thresholds are fractions of Vcc, so the ratio is always 2 and only ln 2 survives. That is why the 555 keeps its frequency steady (typically within about 1% per volt) as the battery sags, as long as you stay inside the datasheet's supply range.

Worked example with numbers

Take R1 = 1 kΩ, R2 = 10 kΩ, C = 0.1 µF.

• t_high = 0.693 × 11 kΩ × 0.1 µF = 0.762 ms
• t_low = 0.693 × 10 kΩ × 0.1 µF = 0.693 ms
• T = 1.455 ms, so f ≈ 687 Hz (the 1.44 shortcut gives 686 Hz)
• Duty = 11/21 = 52.4%

Now see the design trade. To hit exactly 1 kHz with a 1 µF-class capacitor you would solve for (R1 + 2R2) = 1.44 / (f·C), and pick R1 as small as practical so the duty cycle approaches 50%. R1 has a floor: pin 7 sinks current through R1 when the transistor is on, and datasheets recommend keeping R1 above roughly 1 kΩ so you do not overstress the discharge transistor at higher Vcc.

Why you cannot go below 50% (and the diode fix)

Because the charge path includes R1 + R2 and the discharge path only R2, t_high is strictly greater than t_low. The duty approaches 50% only when R2 ≫ R1. To get a true 50% or a duty below 50%, put a signal diode (1N4148) across R2, anode toward pin 7's side of the capacitor path. Charging current now flows through R1 and the diode, bypassing R2, and discharge still goes through R2:

t_high ≈ 0.693 · R1 · C
t_low  ≈ 0.693 · R2 · C
D = R1 / (R1 + R2)

Set R1 = R2 for 50%. Remember that the diode drops about 0.6 V, which shifts effective thresholds slightly, so expect a few percent error at low Vcc. An alternative is to run the 555 at twice the target frequency and divide by two with a toggle flip-flop, which gives an exact 50% regardless of the RC ratio. This divider trick is a common interview follow-up, and it is the same concept covered in our monostable 555 article, where only the discharge/trigger arrangement changes.

Practical issues engineers get asked about

• Bipolar vs. CMOS parts. The NE555 draws about 3-6 mA and its output sags a volt or two from the rail; the CMOS LMC555/TLC555 draws tens to hundreds of microamps, allows megahertz-range operation, and lets you use megaohm resistors. The formulas are identical.
• Capacitor choice. Leakage matters when R is large. Use film or C0G ceramic for accuracy; a Y5V ceramic can move tens of percent with bias and temperature, and the frequency moves with it. Electrolytics are poor timing caps.
• Pin 5. Decouple the control-voltage pin with ~10 nF. Driving it changes both thresholds, which turns the astable into a voltage-controlled oscillator (PWM or FM generator).
• Supply glitches. The bipolar 555 crowbars the supply briefly on each output transition, so add 100 nF right at pin 8.
• Tolerance budget. With 5% resistors and a 10% capacitor, expect around 15% frequency spread. Real products trim or use a crystal-based clock.

Key fact: the 555 is a relaxation oscillator, so its accuracy is set by the RC components and the 2:1 threshold ratio, not by the chip. The comparator offsets and divider matching add roughly 1-2% on top.

Simulating it before you build

In industry you would check this in SPICE: Cadence PSpice/Spectre, Siemens Questa ADMS or the free ngspice all ship 555 behavioural models. Run a transient analysis of at least ten periods, then measure the first period separately: the very first charge starts from 0 V instead of Vcc/3, so it takes longer than the following ones (about 1.1·(R1+R2)·C to reach 2Vcc/3). Forgetting that start-up cycle is a classic reason for hand calculations to disagree with the first scope trace. If you want to push the idea into an IC, the same RC-threshold structure appears as on-chip relaxation oscillators for low-power wake-up timers, which design teams at firms like Avecas sign off with corner and Monte Carlo simulation. For fundamentals-level training, ChipXpert covers the analog front end of this flow.

To extend this, read our Schmitt trigger hysteresis design article, which derives the same two-threshold behaviour with op-amp feedback.

Want to build and simulate oscillators, comparators and timing circuits step by step? Explore the analog tracks in the CourseTron courses.

FAQ

Why is the 555 astable duty cycle always above 50%?

The capacitor charges through R1 + R2 but discharges only through R2, so the high time is longer than the low time by 0.693·R1·C. Adding a diode across R2 removes that asymmetry.

Does the output frequency change with supply voltage?

Only slightly. Both thresholds scale with Vcc, so the voltage ratio is always 2 and the supply cancels. Residual drift comes from comparator offsets and the capacitor.

What is the exact constant, 1.44 or 1.443?

The constant is 1/ln 2 = 1.4427. Datasheets round it to 1.44, which is fine given component tolerances.

How do I get the output exactly 50% duty?

Either use the steering-diode circuit with R1 = R2, or run the astable at double frequency and divide by two with a D flip-flop.