In short: A wire load model is a statistical lookup table that lets a synthesis tool estimate interconnect resistance and capacitance before any routing exists, using only the fanout of a net and the size of the block. It was essential for pre-layout timing at older nodes, but its averaged, location-blind estimates break down below roughly 130 nm, which is why physical synthesis and parasitic extraction into SPEF replaced it at advanced nodes.
A wire load model (WLM) is a table-based method for predicting the parasitic resistance and capacitance of a net before the design has been placed and routed. During logic synthesis there are no physical wires yet, so the tool has no real geometry from which to compute interconnect delay. The wire load model fills that gap by giving a statistical estimate of how long a wire is likely to be, and therefore how much R and C it will add, based purely on how many pins the net drives (its fanout) and the size of the block it lives in.
WLMs are supplied inside the technology .lib (Liberty) file by the foundry or library vendor. Each model holds a curve that maps fanout to an expected wire length, plus per-unit-length resistance, capacitance, and area factors. The synthesis tool reads this, converts the predicted length into an RC load on the driving cell, and feeds that into its delay calculation so it can size gates and buffer paths to meet timing.
At micron and sub-micron nodes down to about 250 nm, gate delay dominated total path delay. Interconnect was comparatively fast, so even a rough wire estimate was good enough to produce a netlist that would still close timing after layout. The wire load model made the classic two-step flow possible: synthesize to a gate netlist with estimated wires, then place and route, then check. Because the estimate was conservative and interconnect was a small fraction of the budget, the gap between the synthesis prediction and the real post-layout numbers was usually tolerable.
The model also kept synthesis fast and self-contained. A table lookup indexed by fanout is almost free to evaluate, so the tool could explore many structural options quickly without the cost of trial placement or routing.
The core idea is simple: more loads on a net generally mean a longer, more branched wire. A WLM encodes this as a monotonic curve. For a net with a given fanout the tool reads an expected length, then multiplies by the per-length capacitance and resistance to get the net's lumped load. Many models also apply a slope factor to extrapolate beyond the largest tabulated fanout point.
A single technology library usually ships several wire load models, each calibrated for a different block size, because average wire length grows with die area:
You can set these explicitly (for example with set_wire_load_model and set_wire_load_mode in a Synopsys flow) when the automatic choice does not match the real block.
As processes scaled past 130 nm toward 90, 65, 45 nm and below, interconnect delay grew until it rivaled or exceeded gate delay. Wires became thinner and taller, resistance per unit length climbed sharply, and coupling capacitance between neighboring wires became a first-order effect. Against this backdrop the central assumption of the WLM — that fanout alone predicts wire load — collapsed:
The industry answer was physical synthesis: the synthesis engine performs a coarse (virtual) placement so it can estimate wire length from real cell positions instead of a table, and iterates placement with optimization. After detailed routing, a parasitic extraction tool computes the true distributed RC and writes it to a SPEF (Standard Parasitic Exchange Format) file. Static timing analysis then runs on those extracted parasitics, giving sign-off accuracy that no fanout table can match.
Contemporary flows from Synopsys (Fusion Compiler, IC Compiler II) and Cadence (Genus, Innovus) are placement-aware end to end. Early RTL exploration may still use a simple metric, but delay estimates quickly move to virtual-route or global-route parasitics, and final timing is signed off on SPEF. In most advanced-node libraries the WLM is either absent or deliberately disabled, and tools warn when a design would otherwise fall back to one.
Real projects and industry tool flows, with certification.
Explore CourseTron Courses →A wire load model is a pre-layout estimate of interconnect based on a fanout-to-length table, used during synthesis when no routing exists. SPEF holds extracted, post-route parasitics computed from the actual physical geometry, used for accurate static timing sign-off. One is a statistical guess; the other is measured from the real layout.
Because they predict load from fanout and block size only, with no placement information. At nodes below roughly 130 nm interconnect delay dominates and nets of equal fanout can vary wildly in length, so a single averaged RC value is wrong for most nets and ignores resistance-dominated and coupling effects entirely.
Wire load mode decides which model applies to a net that crosses hierarchy. Top applies the top block's model, enclosed uses the model of the smallest block that fully contains the net, and segmented uses the appropriate model for each portion of the net as it passes through different blocks.
Rarely, and only for very early or low-effort estimates at mature nodes. Advanced-node flows use physical (placement-aware) synthesis and sign off timing on extracted SPEF. Many modern libraries ship with WLMs removed or disabled to prevent misleading pre-layout numbers.
Related: LEF file in VLSI · the VLSI Glossary · all courses.