LEF file in VLSI

In short: A lef file is an ASCII abstract that tells place-and-route tools the physical shape of a cell or a technology without exposing its internal transistor-level layout. Technology LEF describes the fabrication layers and routing rules, while cell (macro) LEF gives each standard cell or hard macro its size, pins and blockages — together they are the physical library your P&R flow consumes alongside timing Liberty.

What Is a lef file?

A lef file (Library Exchange Format) is a human-readable, ASCII text file that captures the physical abstraction of a VLSI library. Originally defined by Cadence and now a de-facto industry interchange format, LEF lets a design team hand off everything a place-and-route (P&R) engine needs to arrange and wire cells — pin locations, cell dimensions, metal blockages and routing design rules — while deliberately hiding the full polygon-level mask data that lives in the GDSII or OASIS layout.

The key idea is abstraction. A standard-cell NAND gate may contain dozens of polygons across diffusion, poly, contact and metal-1 layers. The router does not need any of that detail; it only needs to know how big the cell is, where its input/output pins sit, and which regions it must avoid. LEF strips the cell down to exactly that information, keeping libraries compact and protecting foundry/IP intellectual property.

Why the LEF Abstraction Matters

Physical implementation tools — Cadence Innovus, Synopsys IC Compiler II and Fusion Compiler, among others — load LEF to build their internal view of the floorplan. Without it, the tool has no notion of where a pin can be accessed or how wide a wire on metal 3 must be. LEF pairs with the Liberty (.lib) timing/power model: Liberty answers “how fast and how power-hungry is this cell?” while LEF answers “how big is it and where do I connect to it?”. You need both for a correct implementation.

• Area-accurate floorplanning — cell SIZE drives row-based placement and utilization estimates.
• Legal routing — layer widths, spacing and pitch come straight from technology LEF.
• Pin access — the router uses PIN PORT geometry to land vias and wires.
• IP protection — the internal transistor layout never leaves the foundry; only the abstract ships.

Technology LEF vs Cell (Abstract) LEF

Although both live in LEF syntax, there are two distinct kinds, and understanding the split is a common interview checkpoint.

Technology LEF

The technology LEF (often tech.lef) is process-specific and shipped once per PDK. It defines the fabric of the node:

• LAYER definitions for routing metals and vias — type, direction (HORIZONTAL/VERTICAL), minimum WIDTH, SPACING, PITCH and resistance/capacitance hints.
• VIA and VIARULE definitions describing legal layer-to-layer cuts.
• SITE definitions — the standard-cell placement grid (row height and the x-step a cell can snap to).
• UNITS and the manufacturing grid.

Cell / Macro (Abstract) LEF

The cell LEF (sometimes called the abstract or standard-cell LEF) contains one MACRO block per cell or hard macro:

• SIZE — the cell’s width × height bounding box.
• SYMMETRY and SITE — how the cell may be flipped/mirrored and which row site it uses.
• PIN blocks — each with DIRECTION (INPUT/OUTPUT/INOUT), USE (SIGNAL/POWER/GROUND/CLOCK) and PORT geometry (rectangles on specific metal layers) marking where to connect.
• OBS (obstruction/blockage) — regions on each layer the router must keep clear, typically internal metal already used by the cell.

For large IP — SRAMs, PLLs, I/O pads — the same abstract concept scales up into a macro LEF, where the MACRO class is BLOCK or PAD rather than CORE, and pin/obstruction geometry can span many layers.

LEF vs DEF — Don’t Confuse Them

LEF and DEF (Design Exchange Format) are siblings but describe different things. The distinction trips up newcomers constantly.

• LEF = the library. Reusable, design-independent. It lists what cells are (their shapes, pins, rules). One LEF set serves every chip on that process.
• DEF = the design. Design-specific. It records how this particular netlist was placed and routed — component instance locations, net routing, die area, rows and pin placement.

A useful mental model: LEF is the catalogue of LEGO bricks (what each brick looks like and where it clips together); DEF is the finished model’s assembly instructions (which bricks went where). The P&R tool reads LEF (plus the Verilog netlist and constraints), produces placement and routing, and can write the result out as DEF for downstream tools or for round-tripping.

How LEF Is Used — and Fixed — in Practice

In a real physical-design flow you point the P&R tool at the technology LEF first, then the cell/macro LEFs. Innovus uses commands like read_physical -lef (or the older init_design with LEF variables); IC Compiler II ingests LEF when a reference library is created or via read_lef in interoperable flows. Common real-world issues and fixes include:

• Pin unreachable / no access point — often the PIN PORT geometry is too small or off-grid for the metal pitch declared in tech LEF. Fix by regenerating a cleaner abstract or widening the port on the access layer.
• LEF/GDS mismatch — the abstract SIZE or OBS disagrees with the real GDS, causing LVS or density surprises at tapeout. Always regenerate LEF from the signed-off layout (e.g. with Cadence Abstract Generator) rather than hand-editing.
• Missing SITE or wrong row height — placement refuses to snap cells; the tech LEF SITE must match the standard-cell library’s intended row.
• Antenna / blockage gaps — incomplete OBS lets the router short against internal cell metal.

Because LEF is plain text, engineers frequently diff versions, grep for a MACRO, or script sanity checks — but production LEF should be generated by the abstract-extraction tool, not written by hand, to stay consistent with the GDS and the signoff rules.

lef file — Interview FAQ

What is the difference between a lef file and a Liberty file?

LEF is purely physical — cell size, pin locations, blockages and routing rules. Liberty (.lib) is purely electrical — timing arcs, delays, setup/hold, and power. P&R needs both: LEF to place and wire, Liberty to time and optimize. Neither contains the other’s data.

What is the difference between LEF and DEF?

LEF describes a reusable library (what the cells and technology layers look like), and is design-independent. DEF describes one specific design’s placement and routing (instance locations, net routing, die area). LEF is an input library; DEF is a per-design physical description the tool can read or write.

What does the OBS section in a MACRO mean?

OBS (obstruction) lists metal regions inside a cell or macro that are already occupied by internal routing or power. The router treats these as keep-out zones so it does not place a wire or via where it would short to the cell’s internal geometry.

Why ship a LEF abstract instead of the full GDS to the P&R tool?

Two reasons: performance and IP. The abstract is far smaller, so the tool loads and operates faster on millions of instances; and it hides the transistor-level layout, protecting foundry and IP-vendor intellectual property while still giving the router everything it needs.

Related: wire load model in VLSI · the VLSI Glossary · all courses.