SPEF file in VLSI

In short: A SPEF (Standard Parasitic Exchange Format) file is the IEEE-1481 ASCII database that captures the resistance and capacitance of every wire in a routed design, so that sign-off static timing analysis can see real interconnect delay instead of idealized zero-delay nets.

Once a design is placed and routed, the logic delay you computed from the standard-cell library is only half the story. The other half lives in the copper: every metal segment has series resistance, every pair of neighbouring wires has coupling capacitance, and every net dumps charge onto ground. A SPEF file is how the extraction engine hands those numbers to the timing tool. If you have ever heard an engineer say "we're doing parasitic-annotated STA," the parasitics almost always arrive as a SPEF.

What problem does SPEF solve?

Before routing, a net is just a logical connection. Delay across it is effectively zero, and a pre-layout timing run using wire-load models is a rough statistical guess. After detailed routing, the physical geometry is known. A parasitic extraction tool — Synopsys StarRC, Cadence Quantus (QRC), or Siemens Calibre xRC — solves the field problem for each net and reduces it to a lumped or distributed RC network. SPEF is the neutral, vendor-independent text format used to carry that network to any downstream tool: PrimeTime, Tempus, or a power/EM checker.

⚡ The format is standardized as IEEE 1481. Because it is plain ASCII and tool-agnostic, a StarRC-generated SPEF can be read straight into Cadence Tempus, and vice versa — that interoperability is the whole point.

What is actually inside a SPEF file?

A SPEF is a structured, human-readable text file. The header declares units and conventions; the body describes each net. Typical blocks:

• Header: *SPEF version, design name, and *T_UNIT, *C_UNIT, *R_UNIT, *L_UNIT (e.g. 1 PS, 1 FF, 1 OHM).
• Name map: long hierarchical net and instance names are aliased to short integer keys (*123) to shrink the file. A full-chip SPEF can be gigabytes, so this matters.
• Ports (*PORTS): primary inputs/outputs with direction.
• Per-net *D_NET blocks: the total lumped capacitance, then *CAP (node capacitances and coupling caps between two nodes), *RES (resistors between nodes), and *CONN (which cell pins and vias connect to which internal node).

A minimal net looks like this:

• *D_NET *117 4.82 — net 117 has 4.82 fF total capacitance
• *CAP 1 *117:3 *44:7 0.31 — 0.31 fF coupling cap between a node on net 117 and a node on aggressor net 44
• *RES 1 *117:2 *117:3 12.4 — a 12.4 Ω segment between two internal nodes of net 117

? Coupling capacitance is what makes SPEF powerful for sign-off: those two-node caps are exactly what a tool needs for crosstalk delay and noise analysis. A "grounded-cap-only" (DSPEF-lite) run throws that information away.

Reduction: how big is the RC network?

Extraction tools can emit parasitics at several reduction levels, trading accuracy for file size and STA runtime:

For a modern 7 nm block, an unreduced SPEF might be 30–50 GB; a reduced one that still matches delay within ~1% is a fraction of that. You pick the level with the extraction tool's effort/reduction knob.

Corners: why you have many SPEFs, not one

Resistance and capacitance drift with process and temperature. Copper is more resistive when the wafer etches thin; capacitance rises when dielectric is thick. So extraction is run per RC corner — commonly cmax (worst cap, hurts setup), cmin (best cap, hurts hold), rcmax, and rcmin. Each corner produces its own SPEF, and multi-corner multi-mode (MMMM) STA reads the matching SPEF per scenario. Getting the corner-to-scenario mapping wrong is one of the most common sign-off mistakes.

SPEF vs DSPF (and SPF)

Students constantly confuse these. All three describe parasitics, but at different abstraction levels:

Rule of thumb: SPEF feeds digital timing sign-off; DSPF feeds transistor-level SPICE. DSPF (and its lumped cousin SPF) preserve the actual device netlist so you can re-simulate the extracted circuit, which is why analog and memory designers prefer it. A digital block-level STA run almost never wants DSPF — it would be enormous and slow.

How SPEF fits the sign-off flow

In a PrimeTime sign-off script, you point the tool at the netlist, the .lib timing models, the SDC constraints, and then read_parasitics block.spef.gz. PrimeTime maps every SPEF net to a design net, builds the RC delay (often with an Arnoldi/AWE-style reduced-order model), and reports timing with real interconnect delay and, if coupling is present, crosstalk. The delays and slews it computes are the same ones you would later see in an SDF file handed to gate-level simulation. In fact, SPEF-annotated STA is typically the step that produces the back-annotated SDF.

A clean annotation is non-negotiable: PrimeTime prints an annotation coverage report, and anything below ~100% means nets were extracted but not matched (name-mapping or hierarchy mismatch) — a silent source of optimistic timing. For the deeper mechanics of post-layout timing, see our companion note on static timing analysis basics.

Want to run StarRC extraction and PrimeTime SPEF annotation on a real routed block? The CourseTron VLSI Physical Design & Signoff track walks you through it end to end with industry tools.

Teams building production sign-off flows often pair this training with hands-on tapeout support from Avecas design services, where parasitic-aware closure is part of daily work.

Common pitfalls

• Wrong RC corner for the scenario — e.g. using cmin SPEF for a setup check makes timing look falsely clean.
• Missing coupling caps — grounding all coupling inflates or deflates delay and hides crosstalk.
• Name-map mismatch after an ECO — the SPEF no longer matches the netlist; re-extract.
• Unit confusion — reading a file whose *C_UNIT is fF as if it were pF gives a 1000× error.

FAQ

Is SPEF only for digital designs?

Primarily, yes. SPEF is the standard for digital RC sign-off STA. Analog and custom designers usually extract to DSPF or a SPICE netlist so they can re-simulate transistor behaviour, though SPEF can still describe those nets.

At what stage is SPEF generated?

After detailed routing, when real wire geometry exists. Pre-route timing uses wire-load models or estimated parasitics; the SPEF comes from post-route extraction (StarRC, Quantus, Calibre xRC).

Why are there multiple SPEF files for one block?

Each process/RC corner (cmax, cmin, rcmax, rcmin, etc.) is extracted separately, so MMMC sign-off can apply the correct parasitics to each timing scenario.

What is the difference between SPEF and SDF?

SPEF carries raw R and C parasitics into STA; SDF carries the resulting cell and net delays (already computed) into gate-level simulation. SPEF is an input to timing; SDF is usually an output.