In short: An SDF (Standard Delay Format) file is an ASCII, tool-independent record of the actual cell and interconnect delays extracted after synthesis or place-and-route, which the simulator back-annotates onto a gate-level netlist so your timing simulation reflects real silicon delays instead of unit or zero delays.
Every VLSI engineer eventually hits the same question in an interview: "Your RTL simulation passed, your static timing is clean, but how do you prove the gate-level netlist still works with real delays?" The answer almost always involves the SDF file. It is the bridge between the static timing world and the dynamic simulation world, and understanding it cleanly separates a candidate who has run flows from one who has only read about them.
What exactly is an SDF file?
SDF stands for Standard Delay Format, defined formally in IEEE Std 1497. It is a plain-text file that stores timing data — propagation delays, interconnect delays, timing checks like setup and hold, and even timing-check-related conditions — in a tool-neutral syntax so that a delay calculator (Synopsys PrimeTime, Cadence Tempus, or an implementation tool like Innovus/ICC2) can write it and a simulator (Synopsys VCS, Cadence Xcelium, Siemens Questa) can read it. Because it is standardized, the tool that computes delay and the tool that consumes delay need not come from the same vendor.
A fragment looks like this conceptually: a CELL entry names an instance, an IOPATH describes the delay from an input pin to an output pin, and triplets (min:typ:max) carry the three process corners in one value. For example (IOPATH A Z (0.082:0.115:0.191) (0.090:0.124:0.205)) gives rise and fall delays in nanoseconds for a path through a buffer.
Key fact: SDF delays are always expressed as triplets min:typ:max. A single number like 0.115 is shorthand for 0.115:0.115:0.115. The TIMESCALE in the header (commonly 1ns or 1ps) fixes the units for every number in the file.
Why back-annotation matters
A gate-level netlist on its own simulates with "zero delay" or the library's "unit delay" — logically correct, but timing-blind. That will happily let a signal race through combinational logic and arrive at a flop in the same delta cycle, hiding hold violations and glitches that real silicon would expose. Back-annotation is the act of loading the SDF so that each gate and each net in the simulation now carries its physical delay. Suddenly a 65 ps hold margin that looked fine in STA can be stress-tested against real stimulus, asynchronous resets, and clock-gating behaviour.
How the simulator consumes it
In Verilog you back-annotate using the system task $sdf_annotate, typically inside an initial block or passed on the command line:
initial $sdf_annotate("top.sdf", testbench.dut, , "sdf.log", "MAXIMUM");
The fourth-to-last argument chooses which of the triplet values to apply — MINIMUM, TYPICAL, or MAXIMUM. For setup (max-delay) sign-off you back-annotate the MAXIMUM corner at the slow process/voltage/temperature; for hold checks you use MINIMUM at the fast corner. The library cells must contain specify blocks with named IOPATH and timing-check constructs for the annotation to land — if the names in the SDF do not match the module's specify block, the simulator silently skips them, which is why the log file argument is never optional in practice.
Interview trap: SDF does not create delays; it only overrides the placeholders already present in the cell's specify block. A missing specify path = a dropped annotation = a false "pass". Always grep the SDF log for the annotation count and zero mismatches.
An animated view of delayed propagation
The whole point is visible the moment you watch a transition crawl through a path instead of teleporting. Below, the red edge enters a buffer and the blue edge emerges one IOPATH delay later — the gap is exactly what the SDF encodes.
Cell delay vs interconnect delay
SDF carries two distinct kinds of delay, and knowing the difference is essential once you move from synthesis to post-layout:
- Cell delay — the
IOPATHdelay inside a standard cell, a function of input slew and output load capacitance, read from the.lib(Liberty) NLDM or CCS tables. - Interconnect delay — the
INTERCONNECTconstruct, representing the RC delay of the physical wire between a driver pin and a load pin. Pre-layout this is estimated from a wire-load model (or zero); post-layout it is computed from extracted parasitics.
Those parasitics come from a companion file — the SPEF (Standard Parasitic Exchange Format). In the full flow the extraction tool produces SPEF, the delay calculator combines SPEF with the Liberty models to compute delays, and only then writes the SDF. If you want the deeper story on where those R and C values come from, our SPEF explainer and the STA fundamentals guide are natural next reads.
| Stage | Interconnect in SDF | Typical use |
|---|---|---|
| Post-synthesis | Wire-load estimate / zero | Early GLS, reset & X-propagation checks |
| Post-route (SPEF-driven) | Real extracted RC | Sign-off gate-level timing simulation |
Timing checks, not just delays
Beyond propagation, SDF encodes TIMINGCHECK entries — SETUP, HOLD, RECOVERY, REMOVAL, WIDTH, and PERIOD. During simulation, if a data pin changes within the annotated setup/hold window of a clock edge, the flop model issues a timing violation and often drives an X onto the output. This is how gate-level simulation catches, dynamically, the same hold problems STA flags statically — and sometimes catches things STA misses, such as violations on paths that were falsely declared as false paths. For foundry-grade design services that lean on exactly this correlation between STA and GLS, teams like Avecas treat a clean SDF-annotated run as a tape-out gate.
Common pitfalls engineers hit
- Hierarchy mismatch: the instance path in
$sdf_annotatemust point at the actual DUT scope, or every cell is skipped. - Wrong corner: annotating MAX delays while trying to debug a hold failure — hold needs MIN at the fast corner.
- Negative hold times: SDF legally carries negative setup/hold values; a simulator that clamps them can report phantom violations.
- Ignoring the log: a run that annotates "0 of 48,000 cells" still finishes "successfully" and lies to you.
Want to run this flow hands-on? CourseTron's gate-level simulation & STA track walks you through writing, back-annotating and debugging SDF on a real netlist with VCS and PrimeTime. Explore the VLSI courses →
Frequently asked questions
Is SDF the same as SPEF?
No. SPEF carries raw parasitic R and C values for the interconnect; SDF carries the final computed delays (cell + interconnect) and timing checks. SPEF is an input to delay calculation; SDF is the output that simulators back-annotate.
Can I use SDF with RTL simulation?
Not meaningfully. SDF back-annotation targets a gate-level netlist whose cells have matching specify blocks. RTL has no cell instances to annotate, so SDF is used only in gate-level (GLS) flows.
Which corner should I back-annotate?
Use MAXIMUM (slow corner) for setup verification and MINIMUM (fast corner) for hold verification. TYPICAL is used mainly for functional sanity and power-aware runs, not for sign-off.
Why did my simulation report zero violations even with SDF?
Almost always an annotation failure — mismatched hierarchy, missing specify blocks, or an SDF written for a different netlist. Check the annotation log file: it must report a high match count and no significant mismatches.