In short: Power planning builds a low-impedance power-ground (PG) network of rings, straps and an upper-metal mesh so that every cell sees its rated supply, keeping worst-case IR drop within roughly 5% of VDD and all PG wire current-densities under the foundry's electromigration limits.
Power planning (also called the power delivery network, or PDN) is one of the earliest and most consequential decisions in physical design. Long before a single signal net is routed, the floorplanning engineer must decide how current travels from the package bumps down to the transistors. Get it wrong and no amount of clever place-and-route will save the chip: cells starve, timing collapses under voltage droop, and metal wears out in the field. This article walks through the structure of a real PG network, how the IR-drop budget is set, and why electromigration (EM) quietly dictates strap widths.
Why a Power Network Needs Structure
Current does not arrive at a standard cell for free. It flows through package pins or flip-chip bumps, through the top metal layers, down through vias, and finally into the M1 power rails that feed each row of cells. Every segment of that path has resistance, and Ohm's law (V = I·R) turns that resistance into a voltage drop. In a modern SoC drawing, say, 20 A at 0.75 V, even a few milliohms of path resistance produces tens of millivolts of droop — a huge fraction of an advanced-node supply.
The answer is a hierarchy of conductors that gets progressively finer as it approaches the cells:
- Rings — wide loops of VDD and VSS around the core (and around hard macros) that distribute current to all four edges.
- Straps (stripes) — regularly spaced vertical and horizontal lines on upper metals that carry current from the rings into the core interior.
- Mesh — the grid formed where orthogonal straps on different layers overlap and are stitched with via arrays, giving many parallel paths.
- Standard-cell rails (followpins) — the thin M1 VDD/VSS rails running along every placement row, tapped from the mesh above.
Rings: The First Loop
The core ring surrounds the placeable area and is usually drawn on two thick upper metals (for example M7/M8 in a 28 nm stack, or a redistribution-like top metal in finer nodes) so it can carry the full chip current with little resistance. Macro rings do the same job locally for memories and analog blocks, which have dense, concentrated current demand. A good rule of thumb: size the ring so its share of IR drop is a small part of the total budget — rings are cheap resistance to buy, and skimping here penalizes the whole interior.
Straps and the Mesh
Straps convert the ring's edge supply into interior coverage. They alternate VDD and VSS, run on at least two orthogonal layers, and connect at every crossing through redundant via arrays. The denser the mesh, the lower the effective sheet resistance seen by the cells — but density competes directly with signal-routing resources and adds capacitance. Tuning strap width, pitch and layer assignment is therefore the heart of power planning. In Cadence Innovus this is scripted with addStripe and addRing; in Synopsys IC Compiler II the equivalent is create_power_straps / create_power_ring. Both let you parameterize pitch and set, then iterate against early rail analysis.
A frequent interview question: "Why vias everywhere the straps cross?" Because a single via has a current limit and a non-trivial resistance; via arrays cut resistance and provide EM headroom and redundancy if one via is defective.
The IR-Drop Budget
IR drop is the DC (static) and transient (dynamic) voltage loss between the ideal supply and what a cell actually receives. The budget is expressed as a percentage of VDD and is split between the package/board and the on-die network. A common on-die target is a total IR drop under ~5% of VDD — so for a 0.75 V rail you are defending roughly a 35–40 mV window for static plus dynamic combined.
Static analysis uses average current and the resistive network alone. Dynamic analysis adds switching activity, decoupling capacitance and the package RLC, catching the millisecond-scale droops that cause real silicon failures. Tools such as Synopsys RedHawk-SC / PrimePower, Ansys RedHawk and Cadence Voltus solve the network and produce a voltage heat-map so you can find and reinforce the weak spots. See our deeper treatment in IR drop in VLSI.
| Mechanism | Driven by | First-order fix |
|---|---|---|
| Static IR drop | Average current × network R | Wider/denser straps, more ring metal |
| Dynamic IR drop | di/dt + insufficient decap | Add decoupling caps, spread hotspots |
| Electromigration | Sustained current density J | Widen wire, add via redundancy |
Electromigration on the PG Network
Electromigration is the gradual transport of metal atoms by the momentum of flowing electrons. Above a current-density threshold, metal thins at one end of a wire and piles up at the other, eventually opening a void or shorting through a hillock. Because PG wires carry large, unidirectional (DC) current, they are far more EM-prone than signal wires, which average out with bidirectional switching. Foundries publish a maximum allowed J (A/µm of width, temperature-derated) via Black's equation; the sign-off job is to keep every strap and via below it over the product's lifetime at operating temperature.
Rule of thumb: widening a strap lowers both its resistance (helping IR drop) and its current density (helping EM) at the same time — which is why power planning treats IR and EM as a single joint optimization, not two separate checks.
A Practical Planning Flow
In practice the loop looks like this: estimate chip current from power analysis, draw rings and a first-cut mesh, run an early static rail analysis on the empty floorplan, then re-run after placement and clock-tree synthesis when real switching activity is available. Reinforce hotspots with wider straps or added decap, and verify EM in the same run. Tools like Innovus and ICC2 let you re-generate the mesh in minutes, so several iterations are normal before timing even closes. If you want the full hands-on PD methodology, our physical-design courses run this flow end-to-end on a real block, and teams that need production help often engage a specialist like Avecas VLSI design services.
One more sibling worth reading before sign-off: understanding decoupling capacitor insertion explains how local charge reservoirs flatten the dynamic droops that no amount of static reinforcement can fix.
Ready to build a real PG network yourself? CourseTron's Physical Design track takes you from floorplan to power-grid sign-off with industry tools and real sign-off decks — explore the VLSI Physical Design course →
Frequently Asked Questions
What is a typical IR-drop target in VLSI?
A common on-die sign-off limit is total IR drop under about 5% of VDD, combining static and dynamic components. The exact number is set per project and per voltage domain, and is tighter for low-voltage advanced nodes where the absolute millivolt margin is small.
Why are power straps wider than signal wires?
Straps carry large, sustained DC current. Wider metal lowers resistance (reducing IR drop) and lowers current density (satisfying electromigration limits) simultaneously, so width is the single most effective knob in the PG network.
What is the difference between a ring and a mesh?
A ring is a wide loop that brings current to the edges of the core or a macro; the mesh is the interior grid of orthogonal straps, stitched by vias, that distributes that current to every placement row inside the core.
Which tools analyze the power network?
Industry-standard rail and EM/IR analyzers include Synopsys RedHawk-SC and PrimePower, Ansys RedHawk, and Cadence Voltus. Mesh construction itself is done in place-and-route tools such as Cadence Innovus and Synopsys IC Compiler II.