Decoupling (decap) cells in VLSI

In short: decap cells are filler-like standard cells that place a capacitor between power and ground right beside the logic, acting as a tiny local charge reservoir. They steady the on-chip supply during fast switching, suppressing IR drop and di/dt noise, but they add leakage, so placement is a deliberate power-integrity tradeoff.

What Is decap cells?

Decap cells (decoupling capacitor cells) are special library cells inserted into the standard-cell rows of a digital layout whose only job is to hold charge between the VDD and VSS rails. Functionally they are a MOS capacitor — typically a wide transistor with its gate tied to one rail and source/drain tied to the other — built in the same technology as the logic so they drop into empty row space exactly like filler cells. They carry no logic function and have no signal pins; electrically they look like a small capacitor sitting directly across the local power supply.

The idea comes straight from board-level design, where engineers scatter ceramic decoupling capacitors next to every IC power pin. On-chip, the same principle applies at a far smaller scale: the package and PCB decaps are too far away (electrically) to respond to the nanosecond current spikes a switching gate demands, so the chip needs its own fast, nearby charge store. Decap cells provide it inside the die itself.

Why decap cells matter: IR drop and di/dt noise

When a block of gates switches simultaneously, it pulls a sudden burst of current from the power grid. The grid is not ideal — it has resistance (R) and inductance (L) in the metal, vias, package, and bond wires. Two problems follow:

• IR drop: current flowing through grid resistance produces a voltage drop, so the local VDD a cell actually sees is lower than the rail voltage at the pad. Enough droop slows the gate and can cause setup-timing failures or outright functional errors.
• di/dt (Ldi/dt) noise: a rapid change in current across the grid inductance induces a transient voltage spike, producing supply ringing and ground bounce that corrupt timing margins and signal integrity.

A decap cell sits physically close to the switching logic and discharges its stored charge in the first few picoseconds of the demand, supplying the transient locally before the distant grid, package, and PCB capacitors can react. It effectively low-pass filters the local supply node, flattening the droop and damping the ringing. Because it responds first, it is the chip's fastest tier in a multi-level decoupling hierarchy that runs die → package → board.

How a decap cell is built

Most decap cells are MOS capacitors: a transistor whose gate forms one plate and the inversion/accumulation layer under it forms the other, giving a high capacitance density per unit area. Common variants include:

• Thick-oxide (I/O-oxide) decaps: use the thicker gate oxide of I/O devices for much lower gate-leakage current, at the cost of lower capacitance density and more area.
• Thin-oxide core decaps: higher density using the core transistor oxide, but they leak more through the gate.
• Switched / gated decaps: include a series device so the capacitor can be isolated, limiting the damage if the thin oxide ever shorts and avoiding a dead short across the rails.
• MOM/MIM decaps: metal-finger or metal-insulator-metal capacitors built in the back-end metal stack; they leak almost nothing but offer lower density and consume routing resources.

Modern libraries also ship ESD-aware and antenna-safe decap variants, and many foundries provide decaps with built-in resistance in series to damp resonance rather than create a new RLC peak.

The leakage tradeoff and where to place them

Decap cells are not free. A thin-oxide MOS capacitor has gate tunneling leakage that flows continuously from VDD to VSS, so blanket-filling every gap with decap can measurably raise static (leakage) power — a serious concern in low-power and mobile designs. The engineering goal is therefore the minimum decap that meets the dynamic-voltage-drop (DvD) target, not the maximum the floorplan can hold.

In practice decaps are placed to put charge where current is drawn and where droop is worst:

• Near high-switching-activity blocks, large clock buffers, and clock-gating cells, which cause the sharpest current spikes.
• Around macros, memories, and the clock tree, and in hot-spot regions flagged by a power-grid / IR-drop analysis.
• Spread uniformly as a baseline (replacing ordinary filler) to keep a floor of local decoupling everywhere, then topped up where analysis demands.

A second reason to insert them is purely physical: like filler and tap cells, decaps fill empty row space so the layout satisfies density and continuous N-well/implant-layer rules. Many flows insert decap as the charge-carrying flavor of filler so the same pass serves both DRC and power integrity.

How industry tools handle decap cells

Decap insertion happens late in place-and-route, usually during or after detailed placement and clock-tree synthesis, once switching activity and the power grid are known. Implementation tools such as Cadence Innovus and Synopsys IC Compiler II insert decap and filler cells with dedicated commands, honoring per-cell density caps and keep-out rules. The quality of the result is then judged by dynamic power-integrity signoff:

• Static and dynamic IR-drop (DvD) analysis with tools like Cadence Voltus or Ansys RedHawk-SC models the grid RLC, applies activity-based current, and reports droop maps. Hot spots drive targeted decap top-up.
• Foundry rule decks and the standard-cell library define legal decap variants, their capacitance and leakage, and the maximum contiguous thin-oxide decap allowed (to bound yield risk from oxide shorts).
• Low-power flows weigh the leakage of each decap flavor against its droop benefit, often preferring thick-oxide or switched decaps on always-on rails.

decap cells — Interview FAQ

What is the difference between a decap cell and a filler cell?

Both occupy empty standard-cell row space and have no logic function, but a filler cell only maintains layer continuity and density for DRC. A decap cell adds a real capacitor between VDD and VSS, so it also provides local charge to fight IR drop and di/dt noise. A decap is essentially a filler that does electrical work — which is why it also leaks more than plain filler.

Why not fill the whole die with decap cells?

Because decaps leak. Thin-oxide MOS decaps have continuous gate tunneling current, so blanket insertion inflates static power and can hurt battery life. There is also a yield concern: a large contiguous thin-oxide area raises the chance of an oxide defect shorting the rails. You insert the minimum decap that meets the dynamic-voltage-drop target, concentrated where droop is worst.

At what stage of the flow are decap cells inserted?

Late in physical implementation — typically after clock-tree synthesis and detailed placement, often alongside or after filler insertion, and iterated against dynamic IR-drop analysis. They go in once switching activity and the power grid are known, so you can place them where current demand and droop actually are.

How do you decide where to place decap cells?

Drive it from power-integrity analysis. Run static and dynamic IR-drop (DvD) with a tool like Voltus or RedHawk, locate the droop hot spots — usually near clock buffers, high-activity logic, and macros — and top up decap there, while keeping a uniform baseline of decap filler everywhere for a floor of local decoupling.

Related: tie cells in VLSI · the VLSI Glossary · all courses.