In short: Power gating in VLSI shuts off the supply to idle logic blocks using MTCMOS sleep transistors, eliminating the leakage current that dominates power in advanced nodes. The technique trades a small active-mode IR-drop penalty and controller complexity for large standby-power savings, and it depends on retention registers, isolation cells, and a carefully sequenced power-up to work safely.
Power gating in VLSI is a low-power design technique that disconnects the power supply from a block of logic when that block is not in use, so it draws almost no current while idle. Unlike clock gating, which only stops switching (dynamic) power by freezing the clock, power gating attacks static leakage power — the current that flows through "off" transistors even when nothing is toggling. As transistors shrank below 90 nm, sub-threshold and gate leakage grew until leakage became a dominant share of total chip power, and simply gating the clock was no longer enough.
The idea is to insert a high-threshold-voltage (high-Vt) switch transistor between the real power rail and the logic's local rail. When the block sleeps, the switch is turned off, collapsing the local rail and cutting leakage by one to three orders of magnitude. This is the core of the widely used MTCMOS (Multi-Threshold CMOS) style: fast low-Vt logic for performance, slow high-Vt switches for the power network.
A power-gated block runs on a virtual power rail rather than directly on VDD or VSS. A sleep transistor sits between the two and acts as the on/off valve:
When the sleep signal is deasserted, the switch is fully on and the block behaves normally — except that the switch adds series resistance. That resistance causes an IR drop on the virtual rail, slightly lowering the effective supply and degrading delay. Designers size the total switch width (or the number of parallel switch cells) so this drop stays within budget, typically a few percent of VDD, under peak current. Too few switches and the block slows down or fails timing; too many and area and leakage through the switches themselves rise.
There are two structural styles, and modern SoCs almost always use the second:
Switches can also be always-on-buffered for control nets, and designers choose between a single large daisy-chained enable or a staged enable to manage rush current.
Collapsing a rail destroys the state inside the block, so power gating needs support cells to stay functional:
The power-up sequence is the most failure-prone part. A large block switched on instantly draws a huge inrush (rush) current as all the decoupling and gate capacitance recharges, which can cause a supply droop that corrupts neighboring always-on logic. Flows therefore use a two-stage wake: a small set of "weak" switches turns on first to pre-charge the rail gently, then the full "strong" switches engage. A typical safe order is: assert isolation → save state → turn switches off (sleep); and on wake, turn switches on (weak then strong) → wait for rail to settle → restore state → release isolation.
Power intent is described separately from the RTL in a power format file — IEEE 1801 UPF (Unified Power Format) or Cadence CPF. The designer declares power domains, supply nets, power switches, isolation and retention strategies, and the states a block may occupy. Synthesis and place-and-route tools then read that intent and automatically insert switch cells, isolation cells, retention flops, and always-on buffers — the RTL itself is not rewritten.
During implementation the tools build the switch fabric, run power-switch-aware placement and routing, and perform rail (IR-drop) analysis on the virtual rails to confirm the switch count meets the droop budget. Power-aware (low-power) verification checks that isolation and retention are present on every crossing and that illegal power-state combinations cannot occur, while UPF-aware simulation models the X-propagation of a collapsed rail so bugs show up before silicon.
Want to insert and verify sleep transistors, UPF power domains, and retention in a real tool flow?
Explore the Physical Design Course →Clock gating stops the clock to idle logic, removing dynamic (switching) power but leaving the block powered and still leaking. Power gating disconnects the supply entirely through sleep transistors, removing the static leakage power as well. Clock gating is cheap and fine-grained; power gating saves far more in standby but needs retention, isolation, and controlled sequencing.
A high threshold voltage minimizes the leakage through the switch itself while the block is off, which is the whole point of gating. The penalty is that the switch is slower and has series on-resistance, producing an IR drop on the virtual rail. Sizing the total switch width (number of switch cells) balances acceptable active-mode droop against area and switch leakage.
Retention registers preserve selected state across a power-down using a small always-on latch controlled by save/restore signals. You need them whenever the block must resume quickly to its prior state rather than being fully reset — for example, configuration registers or a CPU context that must survive a sleep cycle.
When a block's rail collapses, its outputs float to undefined levels. If those nets feed always-on logic, they can cause short-circuit (crowbar) current and corrupt downstream state. Isolation cells clamp the outputs to a safe known value, and they must be enabled before the switches turn off and released only after the rail is stable on wake.
Related reading: continue with the antenna effect in VLSI, brush up terms in the VLSI Glossary, and practice with our Physical Design Interview Questions.