In short: On chip variation (OCV) in VLSI is the fact that identical transistors and wires on the same die behave slightly differently because of process, voltage and temperature spread. Static timing analysis models this by derating path delays, so a setup or hold check passes only if it still holds after launch and capture paths are pushed in opposite, pessimistic directions.
On chip variation (OCV) in VLSI refers to the deviation in delay between nominally identical cells and interconnect located on the same silicon die. Two inverters drawn from the same library, placed a few micrometres apart, will not switch in exactly the same time. The causes are physical: random dopant fluctuation, line-edge roughness, gate-length and oxide-thickness spread, local supply (IR) droop, and on-die temperature gradients. Collectively these are the sources of process, voltage and temperature (PVT) variation that a single corner cannot capture.
Timing signoff would be meaningless if we assumed every gate ran at the same speed. OCV analysis forces the static timing analysis (STA) engine to assume that the launch clock path and the data path might be fast while the capture path is slow (or the reverse), so that the worst realistic skew between two related paths is checked rather than an optimistic average.
Every flip-flop-to-flip-flop timing check compares two paths that share part of the clock tree. For a setup check, late data is the danger, so STA makes the launch path slow and the capture path fast. For a hold check, early data is the danger, so the launch path is made fast and the capture path slow. OCV is applied as a multiplier (a derate) on cell and net delays to create this split.
A typical flat-OCV setting might derate the late path by +5% and the early path by -5%. Because the launch and capture clock paths may reconverge at a common ancestor, a naive derate would double-count variation on the shared portion. The fix is Clock Reconvergence Pessimism Removal (CRPR), which credits back the derate applied to the common clock segment so the check is pessimistic only where the paths actually diverge.
The original and simplest method, a fixed early/late multiplier set in the SDC or tool command (for example set_timing_derate). It is easy but heavily pessimistic on long paths, because it assumes variation never averages out.
Advanced OCV makes the derate depend on two things: the logic depth (number of stages in the path) and the physical distance (bounding-box spread of the cells). A deeper path gets a smaller per-stage derate because random components of variation cancel as stages add, and a path spread across the die gets a larger derate for systematic gradients. AOCV reads this from a lookup table characterised per library and node.
Parametric OCV (also called statistical OCV, or LVF-based signoff) treats each cell delay as a statistical distribution rather than a single number, usually captured as a standard-deviation coefficient in a Liberty Variation Format (LVF) file. The tool then performs a statistical sum of variances along the path and derives an effective derate for a chosen sigma (commonly 3 sigma). POCV is the least pessimistic and the most accurate method, and is standard practice at 16nm/7nm and below.
In Synopsys PrimeTime, flat derating uses set_timing_derate, AOCV is enabled with read_aocvm plus timing_aocvm_enable_analysis, and POCV is driven by LVF data with set_timing_derate -pocvm and read_ocvm. In Cadence Tempus/Innovus, the equivalents are set_timing_derate, SBOCV/AOCV library loading, and set_analysis_view with POCV LVF enabled. CRPR is on by default in both and is reported as "clock reconvergence pessimism" in the slack breakdown. The engines read the library variation data, compute per-arc effective derates, and report the derate actually used in each path, which you should always inspect in the timing report rather than trusting the global setting.
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Explore the Physical Design Course →Setup fails when data arrives too late, so STA slows the launch/data path and speeds the capture clock. Hold fails when data arrives too early, so it speeds the launch/data path and slows the capture clock. The opposite derating creates the worst-case skew for each check.
Clock Reconvergence Pessimism Removal credits back the derate applied to the portion of the clock tree shared by launch and capture paths. Without it the same physical gates would be counted as both fast and slow, adding pessimism that does not exist in silicon.
Flat OCV uses one fixed derate for all paths. AOCV scales the derate by logic depth and physical distance, so a long, deep path gets a smaller per-stage derate because random variation statistically cancels across many stages.
AOCV is table-based and derives a single derate from depth and distance. POCV is statistical: it models each cell delay as a mean with a sigma (from LVF data) and performs a root-sum-of-squares along the path, giving a more accurate, less pessimistic result at advanced nodes.
Related reading: Antenna Effect in VLSI, the VLSI Glossary, and Physical Design Interview Questions.