Metal fill in VLSI

In short: Metal fill inserts dummy metal into empty regions so each layer meets foundry density rules, which keeps chemical-mechanical polishing (CMP) flat and dishing-free — but that extra copper adds coupling capacitance, so modern flows prefer timing-aware, context-aware fill (often grounded) rather than naive floating fill.

Every advanced-node tapeout ends with a step that looks cosmetic but is quietly critical: dropping thousands of tiny dummy metal shapes into the gaps between your real wires. This is metal fill (also called dummy fill or metal density fill). Skip it and the foundry DRC deck rejects the design; do it carelessly and you corrupt the timing you spent weeks closing. This article explains why fill exists, how density and CMP physics drive the rules, the floating-versus-grounded trade-off, and how fill perturbs timing and signal integrity.

Why metal fill exists: the CMP planarity problem

After each metal layer is patterned, the wafer surface is uneven — tall stacks of copper sit next to empty field. Before the next layer can be deposited and lithographically printed, that surface must be planarized by chemical-mechanical polishing. CMP uses a rotating pad plus an abrasive, chemically active slurry to grind the surface flat. The problem is that polish rate depends on the local pattern: soft copper erodes faster than the surrounding dielectric.

Two defects dominate. Dishing is the cupping of a wide copper line as its center polishes below the dielectric edges. Erosion is thinning across a dense array of fine lines where the dielectric between them wears away. Both leave the surface non-planar, which ruins depth-of-focus for the next layer's lithography and changes the final conductor thickness — directly altering resistance and capacitance.

Key fact: CMP sensitivity is why foundries specify a window-based density rule. A typical rule checks metal density inside a sliding window (for example 50 µm × 50 µm, stepped by half the window) and demands it stay between roughly 20% and 80% on every metal layer. Fill brings the sparse windows up to the floor.

Density rules in practice

Density checks are enforced by physical-verification tools — Siemens Calibre, Synopsys IC Validator, or Cadence Pegasus — reading the foundry's qualified rule deck. Beyond the simple min/max floor, advanced nodes add a gradient (density-difference) rule: adjacent windows cannot differ by more than, say, 15–20%, because a sharp density step still causes a local polish-rate discontinuity even when both windows individually pass.

• Min density (e.g. 20%): prevents erosion of sparse regions.
• Max density (e.g. 80%): leaves slurry clearance so dense arrays don't over-polish.
• Gradient: bounds window-to-window variation for uniform planarity.
• Per-layer: lower metals (thin, tight pitch) use small fill shapes; thick upper/RDL layers use larger fill and often slotting of wide metal.

Floating vs grounded fill

This is the decision that most affects electrical behavior. A fill shape can be left electrically isolated (floating) or tied to a power/ground net (grounded, sometimes called tied or connected fill).

• Floating fill is cheap to insert, adds no routing, and is easiest to make density-legal. Its drawback: a floating conductor couples capacitively to nearby signals and acts as a series of coupled parasitics whose voltage swings with its aggressors. Extraction treats it as a floating node, which complicates accuracy and can worsen crosstalk because the island can transfer charge between two signals.
• Grounded fill ties each shape (through vias to a lower rail) to VSS/VDD. It behaves as a fixed-potential shield: it still adds capacitance to ground, but it does not couple two signals to each other, so it is far better for crosstalk and gives cleaner, more predictable extraction. The cost is via area, routing resources, and more complex insertion.

Timing and signal-integrity impact

Fill is never electrically free. Every added shape increases the total capacitance seen by neighboring nets. On a long, lightly loaded net the extra coupling and ground capacitance can add meaningful delay — a few picoseconds per stage on a critical path is common at 7 nm, and on an aggressive path that can be the difference between meeting and missing setup. Fill also changes crosstalk: floating fill tends to increase coupling-induced noise and delta-delay, whereas grounded fill reduces them.

Key fact: This is why fill must be extracted. The post-fill parasitics feed into a SPEF file, and static timing analysis is re-run on that SPEF. A design signed off on a pre-fill netlist is not signed off — the golden STA must see the as-fabricated capacitance.

Best-practice flows therefore do fill late and intelligently:

• Timing-aware / net-aware fill: tools (Cadence Innovus, Synopsys IC Compiler II/Fusion Compiler) keep a keep-out halo around critical nets so fill is not dropped tightly against sensitive wires.
• Grounded over floating on signal-dense blocks to bound crosstalk, accepting the via overhead.
• Re-extract and re-run STA after fill, closing any new violations before tape-out.

If you want the end-to-end picture of how parasitics propagate from layout to sign-off, our companion note on parasitic extraction walks through the RC model that fill directly perturbs. For teams moving from academic flows to production tapeouts, the physical-design services at Avecas handle fill, CMP sign-off, and SI closure on real foundry PDKs.

Common pitfalls

• Running fill before CTS/route freeze — any ECO rip-up invalidates it.
• Forgetting antenna and via-density rules that fill itself can trigger.
• Letting floating fill touch clock or high-speed differential nets.
• Signing off timing on the pre-fill SPEF.

Want to run density fill, CMP checks, and post-fill STA hands-on in a real PDK? The CourseTron Physical Design track takes you from floorplan to GDS sign-off — explore our VLSI courses. Prefer instructor-led cohorts? See the programs at ChipXpert.

FAQ

Is metal fill done automatically or manually?

Almost always automatically. Place-and-route tools (Innovus, IC Compiler II) and signoff tools (Calibre, Pegasus) insert fill using the foundry rule deck. Manual touch-up is rare and limited to sensitive analog or RF regions.

Does metal fill change my timing sign-off?

Yes. Fill adds capacitance, so you must re-extract parasitics into a SPEF and re-run static timing analysis on the post-fill design. The pre-fill timing is optimistic and not valid for tape-out.

Should I use floating or grounded fill?

Grounded fill is electrically safer — it shields signals and avoids relaying crosstalk — but costs vias and routing. Floating fill is simpler and cheaper. Signal-dense or SI-critical blocks favor grounded; non-critical regions often use floating.

What happens if I skip metal fill?

The foundry density DRC fails and the design will not be accepted. Even if forced through, CMP dishing and erosion would leave a non-planar surface, degrading lithography and yield.