In short: A level shifter cell translates a logic signal from one voltage domain to another so a receiver can interpret it correctly, with low-to-high shifters needing a cross-coupled pull-up to rebuild the full swing and high-to-low shifters being far simpler — and both must be physically placed inside the receiving (destination) power domain.
Modern SoCs run dozens of independent voltage islands: a CPU cluster at 0.72 V, an always-on domain at 0.6 V, I/O at 1.8 V, a DDR PHY at 1.1 V. Whenever a net crosses from one of these rails to another, a plain wire is not enough. The logic "1" on the sending side may look like an undefined or leaky level on the receiving side. The level shifter cell is the dedicated standard cell that fixes this. If you interview for a physical-design or low-power role, expect to be asked exactly how it works and where it goes — getting this wrong produces chips that burn crowbar current or fail at low voltage.
Why a voltage domain crossing breaks without a shifter
Consider a gate powered at VDDL = 0.6 V driving a gate powered at VDDH = 1.0 V. The driver's output high is only 0.6 V. The receiving inverter's PMOS has |Vth| around 0.3–0.4 V, so a 0.6 V input relative to its 1.0 V source means the PMOS gate-source overdrive is only ~0.4 V — the PMOS never fully turns off. Both transistors conduct simultaneously, so a DC crowbar (shoot-through) current flows continuously. On a block with thousands of such crossings this can add milliamps of static leakage and, worse, leave the logic level ambiguous. The level shifter removes this by actively regenerating a clean full-rail signal.
Rule of thumb: you need a level shifter whenever the ratio of the two supplies, or their absolute difference, is large enough that the receiver cannot cleanly resolve the driver's output — in practice, almost always for low-to-high and for any crossing greater than roughly 100–200 mV.
Low-to-high: the cross-coupled shifter
Going from a low rail up to a high rail is the hard case, because the input swing is too small to directly drive the high-rail PMOS. The classic solution is a differential cross-coupled (half-latch) structure: two NMOS input transistors driven by the input and its inverse pull down two nodes, and a pair of cross-coupled PMOS devices powered by VDDH latch whichever side is pulled low, regenerating a full 0-to-VDDH output. The input inverter that generates the complement runs on VDDL; the latch runs on VDDH — so the cell needs both supplies routed to it.
Sizing matters: the NMOS devices must be strong enough to overpower the latching PMOS and flip the node, otherwise the cell gets stuck. This "contention" during switching is why low-to-high shifters are slower and larger than a buffer, and why libraries characterize them carefully across voltage/temperature corners in Synopsys Liberty (.lib) files.
High-to-low: the simple case
Coming down from a high rail to a low rail is trivial by comparison. A 1.0 V input easily drives a 0.6 V inverter — the input already exceeds the receiver's rails, so the signal is strong. A high-to-low shifter is often just a VDDL-powered inverter (or buffer) whose input tolerates the higher-voltage swing. The main concern is that the input must not exceed the gate-oxide reliability limit of the thin-oxide low-voltage devices; where the high rail is much larger (e.g. 1.8 V I/O into a 0.9 V core), thick-oxide or dual-oxide shifter variants are used.
Enable level shifters and power gating
In power-gated designs a domain can be switched off entirely. If an "off" domain feeds a live one, its output floats — the receiver needs a defined value. This is where enable level shifters (level-shifter-with-isolation) combine both functions: they clamp the output to a known 0 or 1 when the enable is deasserted, and shift the voltage when active. When only the clamp is needed without a voltage change, a plain isolation cell is used instead — see our deeper treatment in isolation cells in VLSI. The two are frequently confused in interviews; the distinguishing question is "does the voltage change?" and "does a domain go fully off?".
| Type | Direction | Structure | Needs both rails? |
|---|---|---|---|
| Low-to-high | VDDL → VDDH | Cross-coupled PMOS latch | Yes |
| High-to-low | VDDH → VDDL | Single inverter/buffer | Usually one |
| Enable LS | Either + gating | Shifter + clamp | Yes + enable |
Placement rules: destination domain, always
The single most-tested placement rule: a level shifter is placed in the domain of its output (the receiving/destination domain), because its regenerating logic must be powered by the rail of the signal it produces. The UPF/CPF power intent file declares the crossing, and tools such as Cadence Innovus, Synopsys IC Compiler II, or Siemens Calibre's checks enforce that every multi-voltage net has a correctly oriented, correctly placed shifter. Common gotchas:
- Always-on routing: the "high" supply pin of a low-to-high shifter often must be an always-on rail, routed on a special power mesh so the cell keeps working when its source domain sleeps.
- Buffering distance: because shifters are slow, placing them far from either the driver or the receiver bloats timing; most flows restrict them to a legal region near the domain boundary.
- No shifter on same-voltage crossings: inserting one where supplies are equal wastes area and delay — UPF "related supply" checks catch redundant insertions.
- Back-to-back shifters for a two-step crossing (e.g. 0.6→0.9→1.2) are sometimes required when a single cell cannot span the ratio reliably.
Interview nugget: "Where does a low-to-high level shifter sit?" → In the high (destination) voltage domain, on an always-on supply if the source domain can be powered down.
Verification teams at design-services houses like Avecas VLSI design services routinely audit these insertions against the UPF before signoff, since a single mis-oriented shifter can corrupt an entire power-domain interface. To practise the full low-power flow hands-on, explore our CourseTron VLSI courses and the companion article on multi-voltage design with UPF.
Watch the signal cross domains
Ready to design real power-domain interfaces and ace low-power interview rounds? Join the CourseTron Physical Design & Low-Power VLSI course — includes a UPF-driven lab that inserts and verifies level shifters end-to-end. For instructor-led corporate training, see ChipXpert's VLSI training programs.
Frequently Asked Questions
Why is a low-to-high level shifter larger than a high-to-low one?
Because it needs a cross-coupled PMOS latch plus a complement-generating inverter and careful NMOS sizing to win the switching contention, whereas a high-to-low path is typically a single inverter — the small input swing simply cannot drive a high-rail PMOS directly.
In which power domain should a level shifter be placed?
In the destination (output/receiving) domain, since the cell's regenerating logic must be powered by the rail of the signal it produces. If the source domain can be powered down, the shifter's supply is usually an always-on rail.
What is the difference between a level shifter and an isolation cell?
A level shifter translates voltage between domains that stay powered; an isolation cell clamps a signal to a known value when its source domain is switched off but does not change voltage. An enable level shifter combines both functions.
How are level shifters specified in a design flow?
Through the UPF (IEEE 1801) or CPF power-intent file, which declares each voltage crossing; tools like Synopsys IC Compiler II and Cadence Innovus then insert and legalize the cells, and verification confirms orientation and placement.