In short: An isolation cell clamps the output of a powered-down block to a known logic value (0 or 1) before its supply collapses, so a floating, indeterminate signal never corrupts a neighbouring always-on domain — and UPF describes exactly which signal, which clamp value, and which enable timing the tool must honour.
When a design uses power gating, whole blocks of logic get their supply switched off to kill leakage. That is wonderful for battery life, but it creates a nasty electrical problem: the moment a domain loses power, every signal it drives stops being a clean 0 or 1 and drifts into an undefined, floating state somewhere between the rails. If that floating net feeds a still-powered block, it can cause crowbar current in the receiving gate, metastability, or simply garbage logic. Isolation cells exist to stop exactly this. They are, in practice, one of the most interview-tested concepts in low-power physical design, so it pays to understand not just what they do but why and when.
What problem are we actually solving?
Consider a mobile SoC where a camera ISP sits in a switchable domain VDD_ISP and the always-on controller sits in VDD_AON. When the camera is idle, the power management unit cuts VDD_ISP to save roughly tens of milliwatts of leakage. The ISP's output pins — say a 32-bit status bus and a few handshake signals — now float. The always-on controller is still reading those pins. Without protection, the controller's input buffers see an intermediate voltage, both the NMOS and PMOS of the first inverter conduct, and you get a direct path from rail to ground: a static short that can draw milliamps and defeat the entire point of power gating.
Key fact: A floating CMOS input near VDD/2 can turn an inverter into a resistive short drawing 100 µA–1 mA per gate. Multiply by a wide bus and your "powered-off" domain quietly burns more than it saved.
The isolation cell is inserted on the crossing signal, powered by the always-on supply, and holds the net at a deterministic value whenever the driving domain is down.
Clamp-0 vs clamp-1: picking the safe value
An isolation cell is usually just an AND gate (clamp to 0) or an OR gate (clamp to 1), with the isolation enable as one input. The choice is functional, not cosmetic. You pick the value that keeps the receiving logic inactive and harmless while the source is asleep:
- An active-high
reqorvalidhandshake should clamp to 0 so the receiver never sees a spurious request. - An active-low reset or an active-low enable should clamp to 1 so it stays de-asserted.
- A bus feeding an address decoder is usually clamped to a value that selects nothing.
Get this wrong and you have a functionally correct-looking netlist that latches a phantom transaction every time the camera powers down — a bug that only appears in gate-level power-aware simulation, never in plain RTL sim.
Enable timing: the part people get wrong
The single most important sequencing rule in power gating: isolate before you power down, and de-isolate after you power up and restore state. The power management controller must assert ISO_EN while the domain is still fully powered, let it settle, then open the power switches. On wake-up the order reverses: ramp the supply, wait for it to stabilise and for any retention state to restore, release reset, and only then drop isolation.
| Step | Power-down sequence | Power-up sequence |
|---|---|---|
| 1 | Quiesce interface / stop clocks | Turn on power switches, wait for ramp |
| 2 | Assert isolation (ISO_EN=1) | Restore retained state |
| 3 | Assert retention save | Release domain reset |
| 4 | Open power switches (supply off) | De-assert isolation (ISO_EN=0) |
Key fact: The isolation enable must itself be driven from the always-on domain. If you accidentally source ISO_EN from the domain being switched off, it collapses with the supply and your isolation evaporates exactly when you need it — a classic review catch in Synopsys VC-LP / Cadence Conformal Low Power.
How UPF describes all of this
Designers never hand-instantiate isolation cells across a million-gate SoC. Instead the intent lives in a UPF (Unified Power Format, IEEE 1801) file, read by synthesis (Synopsys Design Compiler / Fusion Compiler, Cadence Genus) and place-and-route (IC Compiler II, Innovus). A typical command reads:
set_isolation iso_isp -domain PD_ISP -isolation_power_net VDD_AON -clamp_value 0 -applies_to outputs
set_isolation_control iso_isp -isolation_signal iso_en -isolation_sense high -location parent
This tells the tools which domain to protect, that the clamp cells draw their power from the always-on rail, what value to clamp to, which signal enables them, and physically where to place them (in the parent/always-on region). The verification tools then check that every crossing from a lower-power to a higher-power state is actually isolated — a check you cannot do reliably by eye.
Isolation is closely related to its sibling, the level-shifter cell, which handles a different crossing problem — signals moving between domains at different voltages rather than different on/off states. The two are frequently confused in interviews; remember isolation is about power-down, level shifting is about voltage mismatch, and a cell that does both is a combined enable level-shifter. For the full picture of how both tie into retention and power switches, our structured curriculum walks through a complete UPF-driven flow.
Want to build and verify a real multi-domain UPF flow in Synopsys and Cadence tools, hands-on? CourseTron's low-power VLSI track takes you from RTL to a signed-off power-aware netlist — explore the courses.
Common mistakes and verification
- Wrong clamp value — passes RTL sim, fails in silicon as a phantom transaction.
- Isolation sourced from the gated domain — isolation collapses with the supply.
- Isolation placed inside the switched domain — the cell itself powers off and floats.
- Redundant isolation on same-state crossings — wastes area and adds a gate delay on a timing-critical interface.
Teams running structured low-power sign-off — the kind of design-services discipline you see at Avecas's VLSI design services — treat the UPF and the isolation strategy as a reviewed artifact, not an afterthought, because a single missing clamp can mean a respin.
FAQ
Why not just add a pull-up or pull-down resistor instead of an isolation cell?
A weak pull would eventually settle the net, but it is slow, still allows a floating window, and does not give you a tool-verifiable, deterministic clamp tied to an enable signal. Isolation cells clamp actively and instantly under PMU control.
Is an isolation cell the same as a retention flop?
No. Isolation protects signals leaving a domain so they do not corrupt neighbours. Retention flops preserve a domain's internal state across power-down so it does not have to reboot. They are complementary and usually used together.
Where is the isolation cell physically placed?
In the always-on (parent) region or at the boundary, powered by the always-on rail. Placing it inside the switched domain defeats the purpose because the cell itself would lose power.
Does isolation add timing overhead?
Yes — each isolation cell is an extra AND/OR gate in the path, typically a few tens of picoseconds. On critical interfaces this must be budgeted during timing closure, which is why unnecessary isolation on always-equal-state crossings is actively removed.