In short: Latch-up is a destructive low-impedance short from VDD to ground created when a parasitic PNPN (SCR) structure, inherent to every bulk CMOS inverter, is accidentally triggered into self-sustaining conduction — and it is suppressed mainly through layout discipline, substrate/well contacts, and guard rings.
Latch-up is one of the first failure mechanisms a physical-design or reliability engineer learns to fear, because it can turn a working chip into a smoking package in microseconds. It is not a design bug in the Boolean sense — the logic is perfectly correct — but a consequence of the device physics hiding underneath every bulk CMOS gate. Understanding it is essential context on top of CMOS technology fundamentals, and it shows up constantly in interviews.
Where the parasitic thyristor comes from
Consider a standard CMOS inverter built in a p-substrate with an n-well. The PMOS sits in the n-well; the NMOS sits in the p-substrate. Now look only at the doping regions stacked laterally: the PMOS source (p+) in the n-well, the n-well itself, the p-substrate, and the NMOS source (n+). That is a p-n-p-n sequence — a silicon-controlled rectifier (SCR), exactly the structure of a thyristor. It was never drawn by the designer; it is an unavoidable by-product of placing P and N devices side by side in a shared substrate.
This PNPN can be modeled as two cross-coupled bipolar transistors: a vertical PNP (p+ source / n-well / p-substrate) and a lateral NPN (n+ source / p-substrate / n-well). The collector of each feeds the base of the other. Two resistors matter: Rwell (the n-well resistance to VDD) and Rsub (the substrate resistance to GND). These resistors set the base-emitter bias of the two BJTs.
The triggering condition
Latch-up fires when the loop gain of the two BJTs exceeds unity: βPNP × βNPN ≥ 1. In isolation the transistors are feeble, but a disturbance can forward-bias one base-emitter junction. If a current injected into the substrate develops more than roughly 0.6–0.7 V across Rsub, the lateral NPN turns on, pulling current through Rwell, which turns on the PNP, which injects more current into the substrate — a runaway. Once latched, the SCR holds itself on at a low holding voltage (often ~1–1.5 V) and conducts amps until power is removed. Nothing in the gate logic can stop it.
Rule of thumb: the loop needs a base-emitter drop of only one diode (≈0.6 V). On a 1.2 V or 1.8 V rail, that is startlingly easy to reach if substrate/well taps are sparse.
Common trigger sources
- Overshoot/undershoot at I/O pads — an input driven above VDD or below GND forward-biases a source/drain junction and injects minority carriers. This is the dominant real-world cause and why pad rings are hardened.
- Power-supply transients — fast VDD ramp or a glitch couples displacement current into the wells.
- Radiation / ESD events — a heavy ion or ESD zap dumps charge directly into the substrate (single-event latch-up in space electronics).
- Capacitive coupling from fast-switching high-current nodes.
How layout kills latch-up
Because latch-up is resistive at heart, the cure is to shrink Rwell and Rsub so that injected current cannot build up the 0.6 V needed to turn on a parasitic BJT. The physical-design toolbox:
- Abundant substrate and well taps — dense p+ substrate contacts to GND and n+ well contacts to VDD. Design rules cap the maximum distance from any transistor to a tap (commonly 15–25 µm, tighter near I/O).
- Guard rings — continuous tap rings that surround a device or a whole I/O cell, collecting stray minority carriers before they reach the opposite device.
- Increased n+/p+ spacing — widening the base width of the parasitic BJTs lowers their β.
- Deep n-well / triple-well and guard bands to isolate noisy or high-injection blocks.
- Butted contacts that tie a source directly to its tap, holding the body at the rail.
Verification in the EDA flow
Latch-up is checked in the sign-off DRC deck, not with timing tools. Foundries ship latch-up rules (maximum tap spacing, guard-ring requirements, I/O well-tie rules) that run in Siemens Calibre, Synopsys IC Validator, or Cadence Pegasus. Advanced flows add current-based checks that trace injection paths. Teams building rad-hard parts run dedicated single-event-latch-up (SEL) analysis and may enforce layout that is immune by construction.
Modern SOI and FinFET-on-SOI processes are largely immune because the buried oxide physically breaks the PNPN path — a major reliability motivation for SOI in space and automotive silicon.
| Factor | Raises latch-up risk | Mitigation |
|---|---|---|
| Tap spacing | Sparse / far taps | Dense substrate & well contacts |
| n+/p+ spacing | Close devices, high β | Increase spacing, guard rings |
| I/O overshoot | Pads above VDD / below GND | Hardened pad ring, double guard rings |
| Substrate type | High-resistivity bulk | Epi on p+ substrate, or SOI |
If you are productising a design for automotive or space, pairing a latch-up-aware floorplan with a professional sign-off review — the kind offered through Avecas VLSI design services — is cheaper than a field return. Learn the full physical-design methodology step by step in our CourseTron courses, and see how guard structures interact with ESD protection circuits.
Want to master DRC sign-off, guard rings, and reliability-aware layout hands-on? Enrol in CourseTron's VLSI Physical Design track and build latch-up-immune layouts in a real tool flow.
Frequently asked questions
Does latch-up affect SOI CMOS?
No — in silicon-on-insulator the buried oxide isolates each device so the four-layer PNPN path to the substrate does not exist. This immunity is a key reason SOI is chosen for radiation-hardened and high-reliability designs.
What is the single most common trigger in real products?
Voltage overshoot or undershoot at I/O pads during transients or hot-plug events. An input swung outside the supply rails forward-biases a junction and injects carriers, which is why pad rings get the heaviest guard-ring protection.
Why do guard rings work?
A grounded (or VDD-tied) tap ring provides a low-resistance collection path for stray minority carriers, draining them to the rail before they can develop the ~0.6 V needed to switch on a parasitic bipolar transistor, thereby breaking the SCR feedback loop.
Can latch-up be fixed after fabrication?
Not on a given die — it is a layout property. You can only recover a latched part by cycling power (before the current destroys it). Prevention must happen in layout and verified DRC sign-off.