CMOS Technology

In short: CMOS pairs a PMOS and an NMOS transistor so that one is always off in any steady logic state, letting a gate draw almost no current when idle — which is exactly why it displaced NMOS and bipolar logic to become the dominant process for virtually every modern integrated circuit.

Complementary Metal-Oxide-Semiconductor (CMOS) is the process technology that underpins essentially every digital chip you use today, from the Apple M-series SoC in a laptop to the microcontroller in a washing machine. Its defining trick is deceptively simple: build logic from complementary pairs of transistors so that, in any stable 0 or 1 state, there is no direct conducting path from the supply to ground. The result is static power consumption measured in nanowatts per gate rather than milliwatts — and that single property reshaped the entire semiconductor industry.

The two transistors: NMOS and PMOS

A MOSFET is a voltage-controlled switch. The gate voltage, relative to the source, decides whether a conducting channel forms between drain and source.

• NMOS (n-channel): conducts when the gate is driven high (V_GS > V_th, typically +0.3 to +0.5 V in modern nodes). It is good at pulling a node down to 0 V.
• PMOS (p-channel): conducts when the gate is driven low (V_GS < V_th, a negative threshold). It is good at pulling a node up toward V_DD.

"Complementary" means the two are controlled by the same input but respond oppositely. Tie their gates together, put the PMOS between V_DD and the output and the NMOS between the output and ground, and you have the simplest CMOS gate — an inverter.

How the inverter actually works

Trace the two input states:

• Input = 0 V: the NMOS sees V_GS=0 and stays off; the PMOS sees a large negative V_GS and turns on, connecting the output to V_DD. Output = 1. The only path to ground is through the off NMOS.
• Input = V_DD: the NMOS turns on and pulls the output to ground; the PMOS is off. Output = 0. The only path to V_DD is through the off PMOS.

In both stable states exactly one transistor is off, breaking the supply-to-ground path. A tiny subthreshold leakage still flows (picoamps historically, but significant in aggregate at advanced nodes), yet there is no continuous DC current the way a resistive NMOS load would draw.

Key fact: Classic NMOS-only logic (dominant in the late 1970s, e.g. the Intel 8080-era parts) used a resistive load that conducted whenever the output was low, burning static power on every "0". CMOS eliminates that load entirely.

The dynamic-power picture — where energy really goes

Because static current is near-zero, CMOS energy is dominated by switching. The canonical equation every VLSI interviewer expects you to know is:

P_dynamic = α · C · V_DD² · f

where α is the activity factor (fraction of cycles a node toggles), C the switched capacitance, V_DD the supply, and f the clock frequency. Two consequences fall straight out of it: first, power scales with the square of V_DD, which is why lowering the rail from 1.2 V to 0.8 V is such a powerful knob; second, power is proportional to frequency, which is why clock gating (forcing α→0 on idle blocks) is a first-line low-power technique.

Building real logic: pull-up and pull-down networks

The inverter generalises. Every CMOS gate is a pull-down network (PDN) of NMOS transistors to ground and a pull-up network (PUN) of PMOS transistors to V_DD, and the two are duals: series in one becomes parallel in the other. A 2-input NAND, for example, uses two NMOS in series (output goes low only when both inputs are high) and two PMOS in parallel. This duality is why CMOS is naturally inverting — NAND and NOR are the "cheap" primitives, and synthesis tools from Synopsys Design Compiler or Cadence Genus map Boolean logic onto exactly these standard cells from a foundry library.

Why CMOS won

The low static power is the headline, but it compounds. Low power means less heat, which means you can pack more transistors in the same thermal budget — enabling the density that carried the industry through decades of scaling. CMOS also swings rail-to-rail, giving superb noise margins, and it is manufacturable at extraordinary density. By the mid-1980s these advantages were decisive, and CMOS became the default for microprocessors, memory, and ASICs alike.

Key fact: At deep-submicron nodes the story has partly inverted — leakage (static) power grew as threshold voltages fell, which is why modern designs use high-V_th cells, power gating, and FinFET/GAA structures to recover the original low-static-power promise. Siemens (Calibre) and the foundry DRC decks police these multi-V_th libraries.

Where to go next

Understanding the switch is step one; the next is how these devices are physically built — the n-wells, gate oxides, and ion implants covered in our CMOS fabrication process guide. If you want to see how gates are composed into real cells, read how we reason about static timing analysis on those same standard cells. For hands-on design-rule and layout work, the industry-standard flows are also taught through our design-services partner Avecas VLSI design services.

Want to go from "I understand an inverter" to taping out real logic with Synopsys and Cadence tools? Explore the full VLSI track on our CourseTron courses page.

Frequently asked questions

Why does CMOS consume almost no static power?

In any steady logic state, one of the complementary transistors is always off, so there is no continuous conducting path from V_DD to ground. Power is spent almost entirely during switching, not while holding a value.

What is the difference between NMOS and PMOS?

NMOS conducts when its gate is driven high and is efficient at pulling a node to ground; PMOS conducts when its gate is driven low and pulls a node up to V_DD. They are controlled by the same input but respond oppositely — hence "complementary."

If CMOS is low-power, why do modern chips still run hot?

Dynamic power scales with C·V²·f, and with billions of transistors switching at gigahertz clocks the switching energy adds up. At advanced nodes subthreshold leakage also became a meaningful static component, which designers fight with power gating and multi-threshold libraries.

Is CMOS used only for digital logic?

No. The same CMOS process fabricates analog and RF circuits, image sensors (CMOS sensors), and SRAM memory. Its versatility on a single process is a major reason it dominates mixed-signal system-on-chip design.