In short: A DEF file in VLSI (Design Exchange Format) is an ASCII database that captures the physical implementation of a chip design — component placement, net connectivity, routed wires, pins, blockages and die geometry — for one specific netlist. It pairs with the LEF file, which describes the reusable library and technology abstractions, so together LEF+DEF let EDA tools exchange a complete physical view of the design.
A DEF file in VLSI is the Design Exchange Format representation of a single chip design's physical layout. Originally defined by Cadence as part of the LEF/DEF pair, it is a human-readable ASCII file (conventionally ending in .def) that stores everything about where things are and how they connect for one netlist mapped onto one technology.
Unlike GDSII or OASIS, which carry full polygon geometry for mask generation, DEF is design-specific and instance-level. It names every standard-cell instance, every net, every pin and every routed segment by reference. It does not redraw the internal shapes of a cell — it points to the cell's abstract defined elsewhere. That separation is the whole idea behind LEF and DEF.
Engineers constantly confuse these two formats because they travel together. The distinction is clean once you anchor it:
Think of LEF as the catalogue of parts and the rules for assembling them, and DEF as the assembly instructions for one particular product built from that catalogue.
A DEF file is organized into clearly delimited statements. The important ones, roughly in the order a tool writes them:
The file opens with VERSION, DESIGN
ROWS define the standard-cell placement rows (site name, origin, orientation, step and count), establishing the legal placement grid. TRACKS define routing tracks per metal layer — the x/y grid onto which the router snaps wires.
The COMPONENTS section lists every instance: instance name, its master cell (from LEF), its placement status (PLACED, FIXED, COVER or UNPLACED), coordinate and orientation (N, S, FN, FS, etc.). This is the placement database.
The PINS section describes the design's primary I/O ports — name, associated net, direction, the metal layer and rectangle of the physical pin shape, and its placement on the die edge or inside.
The NETS section is the connectivity heart of the file. Each net lists its connected pins (instance/pin pairs plus any primary pins) and, once routing is done, the ROUTED geometry: the sequence of metal-layer segments and via instances that physically realize the net. SPECIALNETS handles power and ground (VDD/VSS) — wide, often shielded or stripe/ring routing that is treated separately from signal nets.
Additional sections capture BLOCKAGES (placement or routing keep-outs), REGIONS and GROUPS (floorplan fences and soft/hard placement constraints), VIAS (design-specific via definitions), and GCELLGRID for the global-routing grid. The file closes with END DESIGN.
DEF is the common currency that lets physical-design tools interoperate. Because it is open ASCII and instance-level, it is written and re-read at nearly every milestone:
Because every coordinate is explicit, DEF is also perfect for scripted edits: you can parse it, nudge a macro, add a blockage or rip up a net programmatically without a full GUI session.
In Cadence Innovus the commands are defIn to read and defOut (with flags like -floorplan, -routing, -netlist) to selectively dump sections. Synopsys IC Compiler II uses read_def / write_def, and OpenROAD uses read_def / write_def on top of its LEF database. A few practical realities:
Learn LEF/DEF, floorplan and routing hands-on
Explore the Physical Design Course →Not meaningfully. DEF references cell masters, layers, vias and sites by name, and those names are defined in LEF. A reader needs the LEF loaded first; a DEF alone is just a set of names and coordinates with nothing to resolve them against.
NETS carry ordinary signal connectivity and, after routing, thin signal wires. SPECIALNETS carry power and ground — typically wide stripes, rings and rails with explicit widths, shapes and shielding. Tools treat them separately because PG routing follows different width and spacing rules.
No. DEF stores placement and routing by reference — instance locations, net routes as layer segments and vias. The full polygon mask data lives in GDSII or OASIS, produced after sign-off by streaming out the merged LEF+DEF plus cell geometry.
After floorplan (die, rows, macros, pins), after placement (COMPONENTS placed), after CTS, and after detailed routing (complete NETS). Each dump captures the design state at that point, which makes DEF a natural checkpoint and hand-off format.
Related reading: Antenna effect in VLSI · VLSI Glossary · Physical Design Interview Questions.