Clock jitter in VLSI

In short: Clock jitter is the cycle-to-cycle variation in the actual arrival time of clock edges relative to their ideal, perfectly periodic positions. Because it randomly shortens or lengthens the time available between launch and capture flops, jitter directly eats into setup and hold margins and must be budgeted explicitly during static timing analysis (STA).

What is clock jitter?

Clock jitter is the deviation of a clock signal's edges from their ideal, equally spaced positions in time. A perfect clock would place every rising edge at exactly T, 2T, 3T, and so on, where T is the clock period. A real clock, generated by a PLL or DLL and distributed through buffers, wires, and PVT-sensitive gates, places each edge slightly early or slightly late. That timing error, measured in picoseconds, is jitter.

Jitter is fundamentally a temporal phenomenon: it describes how the same clock node moves around in time from one edge to the next (or over a window of cycles). This is what separates it from skew, which is a spatial difference between two different clock endpoints. Jitter is usually treated as a random (and sometimes deterministic) uncertainty on top of the nominal clock.

Where jitter comes from

Jitter is not a single effect but the sum of several physical mechanisms accumulating along the clock path:

• PLL/VCO phase noise — the oscillator that synthesizes the clock has thermal and flicker noise in its control loop, producing random phase wander. This is often the dominant source of jitter on an SoC's reference clock.
• Power-supply noise — IR drop and di/dt noise on the clock buffers modulate their delay. When many flops switch simultaneously, the supply sags and clock edges shift. This supply-induced jitter is a major contributor in large digital designs.
• Thermal and device noise — random noise in transistors adds to edge-crossing uncertainty.
• Crosstalk — aggressor nets coupling into clock wires advance or delay edges depending on switching direction.
• Reference and crystal noise — imperfections in the incoming reference propagate through the PLL.

Jitter vs. skew

These two are constantly confused, so pin them down:

• Skew is the difference in arrival time of the same clock edge at two different sequential elements (launch flop vs. capture flop). It is spatial and, for a given routed design, largely static and deterministic — the clock tree synthesis (CTS) tool works to minimize it.
• Jitter is the variation in arrival time of successive edges at a given point. It is temporal and random. You cannot "route it out"; you can only budget and reduce its sources.

A useful mental model: skew asks "do both flops see the edge at the same moment?" Jitter asks "does this flop see each edge at the right moment, cycle after cycle?"

Types of jitter

• Period jitter — the variation in the length of a single clock period versus the ideal T. This is what most directly attacks a single-cycle setup check.
• Cycle-to-cycle jitter — the difference in length between two consecutive periods. Important for designs sensitive to short-term variation.
• Long-term / accumulated jitter (phase jitter) — how far an edge drifts from the ideal grid over many cycles, dominated by the PLL's random walk.
• Random jitter (RJ) — unbounded, Gaussian, from thermal and shot noise; specified as an RMS value and extrapolated to a target bit-error rate.
• Deterministic jitter (DJ) — bounded and data- or supply-correlated (duty-cycle distortion, inter-symbol interference, crosstalk).

How jitter impacts setup and hold timing

Consider a launch flop clocked by edge n and a capture flop clocked by edge n+1. The data must propagate and settle before the capture edge.

For the setup check, the worst case is when the capture edge arrives early — jitter effectively shortens the available period. If the capture clock edge is pulled in by jitter J, the setup requirement becomes:

• Required time = T − setup − T_skew − jitter

So jitter is subtracted straight out of the data-path budget. A path that passed with zero margin will fail once realistic jitter is included.

For the hold check, launch and capture typically share the same edge, so period jitter largely cancels for a common-clock path — which is why hold is usually far less sensitive to jitter than setup. However, crosstalk-induced and supply-induced jitter that affect launch and capture differently can still degrade hold margin, so tools apply a (usually smaller) hold-side uncertainty.

The practical consequence: jitter sets a floor on the achievable clock frequency. If you want a faster clock (smaller T), the fixed jitter budget consumes a larger fraction of each period, so high-frequency designs are the most jitter-constrained.

How STA tools margin for jitter

Static timing analysis does not simulate every edge; instead it models jitter (and other clock imperfections) as clock uncertainty. In industry flows this is applied with commands such as set_clock_uncertainty in Synopsys PrimeTime or Cadence Tempus, and during synthesis in Design Compiler/Genus.

Key practices engineers follow:

• Separate setup and hold uncertainty. Tools let you set a larger uncertainty for setup and a smaller (or zero) one for hold using the -setup and -hold options, matching the physics above.
• Pre-CTS vs. post-CTS. Before clock tree synthesis, clock uncertainty bundles both expected skew and jitter, because real skew is not yet known. After CTS, the tool computes actual propagated skew from the routed tree, so uncertainty is reduced to just jitter plus a small margin.
• Jitter budget sourcing. The jitter number comes from the PLL datasheet (RMS phase/period jitter), supply-noise analysis, and crosstalk delay analysis. Teams typically convert RMS jitter to a peak value using a sigma multiplier tied to a reliability target.
• On-chip variation (OCV/AOCV/POCV) handles path-dependent delay variation, working alongside the explicit jitter uncertainty rather than replacing it.

The golden rule is that jitter is always applied pessimistically: it is removed from the available margin so the silicon still meets timing under the worst realistic edge placement.

clock jitter — Interview FAQ

What is the difference between clock jitter and clock skew?

Skew is the spatial difference in arrival time of the same clock edge at two different flops and is largely static for a routed design. Jitter is the temporal variation in arrival time of successive edges at the same point and is random. Skew can be positive or negative for a path; jitter is modeled as a pessimistic uncertainty that only reduces margin.

Why does jitter affect setup checks more than hold checks?

A setup check spans two consecutive edges (launch at edge n, capture at edge n+1), so period jitter directly shortens the available window. A hold check usually uses a common edge for launch and capture, so most of the jitter cancels. STA therefore applies a larger setup uncertainty and a small or zero hold uncertainty.

How do you apply jitter in static timing analysis?

Jitter is folded into clock uncertainty with a command like set_clock_uncertainty, typically split into -setup and -hold values. Pre-CTS the uncertainty also absorbs estimated skew; post-CTS, with real propagated skew computed, the uncertainty is trimmed down to the jitter component plus a safety margin.

What are the main sources of clock jitter in an SoC?

The dominant sources are PLL/VCO phase noise, power-supply (IR-drop and di/dt) noise on clock buffers, crosstalk coupling into clock nets, and device thermal noise. Supply noise is often the largest contributor in big digital blocks because simultaneous switching current modulates buffer delay.

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