In short: A PCIe switch is a packet-routing fabric that sits below a root port, taking a single upstream link and fanning it out to many downstream ports so one root complex can reach dozens of endpoints that could never share a physical lane budget directly.
Every modern CPU exposes only a finite number of PCI Express lanes from its root complex, and every root port drives exactly one link. When a design needs more endpoints than the root has ports, or needs to share a limited lane budget across many devices, a PCIe switch becomes the fan-out engine. This article walks through how a switch expands connectivity, how it routes packets, and why its internal virtual-PCI-to-PCI bridges are the mental model you need for both board design and verification.
Why a switch exists below the root port
A root complex might offer, say, 16 Gen5 lanes. You can configure those as one x16 link or split them into x8+x8 or x4+x4+x4+x4 via bifurcation, but each resulting root port still terminates at a single device. If you want to attach an NVMe drive, a NIC, and a GPU behind one x8 root port, bifurcation alone cannot help. A switch takes that one upstream link and presents several independent downstream links, each capable of enumerating as its own device.
A PCIe switch is logically a collection of virtual PCI-to-PCI bridges (vPPBs): one upstream-facing bridge plus one downstream bridge per downstream port, all tied to an internal virtual bus. Software sees ordinary bridges and enumerates them exactly as it would discrete ones.
This is the single most important idea. The switch is not a mysterious black box to enumeration software. The PCIe specification deliberately makes it look like a tree of PCI-PCI bridges so that decades-old legacy PCI enumeration still works. A PCIe root complex walks the hierarchy, assigns bus numbers, and programs each bridge's memory and bus-number windows without needing to know the physical topology at all.
Lane fan-out versus bandwidth
A switch fans out ports, but it does not manufacture bandwidth. Consider a switch with a x8 Gen4 upstream (about 16 GB/s usable after 128b/130b encoding) feeding four x4 downstream ports. The aggregate downstream capacity is 4 × x4 = x16 of potential, but it is all funneled through an x8 uplink. This is deliberate oversubscription, and it is fine when the four drives are rarely busy at once. The switch's internal buffering and arbitration decide who wins when they contend.
| Upstream | Downstream ports | Oversubscription | Typical use |
|---|---|---|---|
| x16 Gen5 | 4 × x4 | 1:1 | Balanced NVMe backplane |
| x8 Gen4 | 4 × x4 | 2:1 | Cost-optimized storage shelf |
| x4 Gen3 | 8 × x1 | 2:1 | Many low-rate peripherals |
How a packet is routed
PCIe is a packet-switched point-to-point protocol. Transaction Layer Packets (TLPs) carry a header that tells the switch how to forward them. A switch uses three routing methods depending on the TLP type:
- Address routing — memory and I/O requests carry a target address. Each downstream bridge holds a programmed address window (base/limit registers). The switch forwards the TLP out of the port whose window contains the address.
- ID routing — completions and configuration TLPs carry a Bus/Device/Function (BDF) identifier. The switch matches the BDF against each bridge's secondary/subordinate bus range and routes accordingly.
- Implicit routing — messages such as INTx or power-management broadcasts follow fixed rules (to root, broadcast downstream, or local).
A downstream request whose address matches none of the downstream windows is forwarded upstream toward the root — this is the default "catch-all" path and is exactly how peer traffic reaches the host or how a misrouted address surfaces as an Unsupported Request.
Flow control, buffering and arbitration
Inside the switch, each port maintains credit-based flow control. The switch only forwards a TLP when the next link has advertised enough credits in the relevant buffer class (Posted, Non-Posted, Completion). When several downstream ports want the uplink at once, a Virtual Channel (VC) arbiter and port arbiter decide ordering, and traffic classes (TC0–TC7) mapped to VCs let a design give, for example, isochronous video priority over bulk storage. Most commodity switches implement only VC0, but the mechanism matters for QoS-sensitive designs.
Advanced features: NTB, SR-IOV and hot-plug
Beyond plain fan-out, switches add value. A Non-Transparent Bridge (NTB) port lets two independent root complexes — two CPUs — share a fabric while keeping separate address domains, which is how many dual-controller storage arrays achieve failover. Downstream ports also support hot-plug, so a drive can be inserted or removed while the system runs, with the switch generating the Presence Detect and attention events. Switches further cooperate with SR-IOV so a single physical endpoint can present many virtual functions to virtualized hosts.
Where engineers meet switches in the flow
If you design or verify PCIe silicon, the switch model drives your testbench. Verification IP from Synopsys VC VIP, Cadence Verification IP, or Siemens (Questa/Mentor) can act as root, switch, or endpoint, injecting malformed TLPs to confirm your design routes, drops, or escalates correctly. Signal-integrity closure of the high-speed lanes is checked with tools like Cadence Sigrity, while logical equivalence and timing use the standard Synopsys and Cadence implementation flows. Teams building this expertise often pair structured training from ChipXpert's protocol and VLSI programs with hands-on lab work.
For the companion piece on what sits above the switch, read our deep dive on the PCIe root complex, and for the enumeration mechanics that program all these bridges, see PCIe enumeration and configuration space.
Want to master PCIe end to end — TLPs, LTSSM, switches and verification? Explore the protocol track on our CourseTron courses page and build interview-ready depth.
Frequently asked questions
Does a PCIe switch add latency?
Yes. Each switch hop adds store-and-forward (or cut-through) latency, typically on the order of 100–150 ns per switch for the TLP to be received, routed, and retransmitted. For latency-critical links like a GPU or a low-latency NIC, designers prefer a direct root-port connection and reserve switches for fan-out where the latency is acceptable.
Is a PCIe switch the same as a PCIe bridge?
Conceptually a switch is built from bridges. A transparent bridge joins two buses and is invisible as a routing device; a switch bundles one upstream bridge and multiple downstream bridges on a shared virtual bus. A single discrete PCI-to-PCI bridge simply connects two segments, whereas a switch provides many-way fan-out.
Can two CPUs share devices through one switch?
Yes, using a Non-Transparent Bridge port. The NTB translates addresses between the two independent host domains so neither root complex tries to enumerate the other's devices, which is the basis for redundant storage controllers.
How does software know a switch is present?
It does not need special knowledge. During enumeration the root complex discovers a chain of PCI-to-PCI bridges, reads their capability structures, and assigns bus numbers and address windows. The switch deliberately presents itself as standard bridges so legacy enumeration code works unchanged.