PCIe Gen3 vs Gen4

In short: PCIe 4.0 doubles the per-lane raw rate from 8 GT/s to 16 GT/s while keeping the same efficient 128b/130b encoding as PCIe 3.0, so a x16 link jumps from ~15.75 GB/s to ~31.5 GB/s usable bandwidth — but that doubling of the Nyquist frequency roughly quadruples channel loss, forcing tighter PCB materials, more equalization, and often retimers.

Same encoding, double the rate

Both PCIe 3.0 and PCIe 4.0 use 128b/130b line encoding. The transmitter groups 128 payload bits into a block and prepends a 2-bit sync header, producing 130 bits on the wire. The overhead is therefore just 2/130 ≈ 1.54%. This is a deliberate break from PCIe 1.x/2.x, which used 8b/10b and paid a brutal 20% encoding tax. PCIe 4.0 did not touch this scheme at all — it is the one knob the standard left alone.

What changed is the unit interval (UI). At 8 GT/s the UI is 125 ps; at 16 GT/s it halves to 62.5 ps. Every bit now occupies half the time, so the fundamental (Nyquist) frequency of the signal doubles from 4 GHz to 8 GHz. That single fact drives almost every engineering consequence discussed below.

Per-lane raw rate: Gen3 = 8 GT/s, Gen4 = 16 GT/s. After 128b/130b encoding, usable payload per lane is 8 × (128/130) ≈ 7.88 Gb/s for Gen3 and ~15.75 Gb/s for Gen4 — before TLP/DLLP packet overhead.

Turning GT/s into GB/s

Engineers constantly confuse the marketing number (GT/s) with deliverable throughput. The chain is: raw rate → remove encoding → that is your usable lane rate. For a x16 link:

• Gen3 x16: 8 GT/s × 16 lanes × (128/130) ÷ 8 = ~15.75 GB/s per direction.
• Gen4 x16: 16 GT/s × 16 lanes × (128/130) ÷ 8 = ~31.5 GB/s per direction.

Real applications see a little less. Transaction Layer Packet (TLP) headers, Data Link Layer Packets (DLLPs), flow-control credits, and ACK/NAK traffic consume a few percent more. A well-tuned NVMe SSD on Gen4 x4 (~7.5 GB/s theoretical) realistically delivers ~7.0 GB/s of sequential read — which is already why Gen4 SSDs feel so much faster than Gen3's ~3.5 GB/s ceiling.

The signal-integrity price of 16 GT/s

Here is the part interview candidates underestimate. Copper trace loss (dielectric + conductor loss) rises with frequency. Moving the Nyquist point from 4 GHz to 8 GHz pushes insertion loss from roughly −0.3 to −0.5 dB/inch on standard FR-4 to well over −1 dB/inch at 8 GHz. The PCIe 4.0 base spec budgets about −28 dB of total channel insertion loss at Nyquist, versus roughly −22 dB for Gen3 — but you are spending that larger budget across a channel that attenuates far more steeply.

The practical effects:

• Shorter reach. A Gen3 trace that ran 20 inches on cheap FR-4 may only run 8–10 inches at Gen4 before the eye closes.
• Better laminates. Designers switch from standard FR-4 to low-loss materials (Megtron-6, Isola I-Tera) with a lower dissipation factor (Df).
• Retimers, not just redrivers. At Gen4, passive redrivers often aren't enough; clock-recovering retimers (from Astera Labs, TI, etc.) regenerate the signal mid-channel.
• Stronger equalization. Both generations use TX de-emphasis, RX CTLE and DFE, but Gen4 leans much harder on them to reopen a collapsed eye.

Rule of thumb: doubling the data rate roughly doubles loss in dB terms at the new Nyquist — which in linear amplitude terms means the received signal can be several times smaller, demanding far more aggressive equalization to recover the same bit-error rate (target BER 1e-12).

Why eye diagrams get scary

Serial-link designers live in the eye diagram — overlaid bit transitions showing how much clean "open" area the receiver has to sample. With the UI halved to 62.5 ps, the horizontal eye opening shrinks, jitter eats a larger fraction of the budget, and inter-symbol interference (ISI) from the lossier channel smears transitions. Teams verify this with tools like Keysight ADS or Cadence Sigrity for channel simulation, and Synopsys HSPICE for SerDes modeling, then confirm on real silicon with a high-bandwidth real-time scope running compliance masks.

Side-by-side comparison

What stayed the same (and what Gen5 changed)

Crucially, both Gen3 and Gen4 remain NRZ (non-return-to-zero) signaling — two voltage levels, one bit per symbol. Gen4 bought its bandwidth purely by clocking faster, which is why the signal-integrity problem is so acute. PCIe 5.0 kept NRZ at 32 GT/s (even harder channels), and only PCIe 6.0 broke the pattern by moving to PAM4 (four levels, 2 bits/symbol) plus FLIT-mode and forward error correction. Understanding that Gen3→Gen4 was "same encoding, same modulation, double the clock" is the clean mental model that makes the whole roadmap click. If you want the lane-width side of the story, see our companion piece on how PCIe lanes work, and for the next step up, Gen4 vs Gen5.

Want to design and validate high-speed serial links hands-on — eye diagrams, equalization, and channel compliance? Explore the SerDes and protocol modules in our CourseTron course catalog. For industry-grade board and SI design services, our partner Avecas design services takes PCIe layouts from schematic to signoff.

FAQ

Is PCIe 4.0 backward compatible with PCIe 3.0?

Yes. PCIe is fully backward and forward compatible. A Gen4 card in a Gen3 slot (or vice versa) negotiates down to the lowest common rate during link training, so it simply runs at Gen3 speeds.

Why didn't PCIe 4.0 change the encoding to gain more bandwidth?

128b/130b is already extremely efficient at ~1.54% overhead — there was little left to win. Doubling the clock rate was the cheaper path to 2x bandwidth, with the cost paid in signal integrity rather than encoding changes.

Do I always need a retimer for PCIe 4.0?

No. Short, well-designed channels on low-loss material can meet the Gen4 loss budget without one. Retimers become necessary on longer traces, backplanes, or cable runs where the ~−28 dB budget is exceeded.

What is the real-world speed difference for an SSD?

A Gen3 x4 NVMe drive tops out near 3.5 GB/s sequential read; a Gen4 x4 drive reaches roughly 7 GB/s — close to double, matching the theoretical rate change.