In short: PCIe moves data through three cooperating layers — the Transaction Layer builds and routes TLP packets, the Data Link Layer guarantees their reliable, in-order delivery with sequence numbers and ACK/NAK, and the Physical Layer serializes those bytes onto differential lanes using encoding, scrambling and embedded clocking.
PCI Express (PCIe) replaced the old parallel PCI bus with a point-to-point, packet-switched, serial fabric. If you have ever probed a link that trains to x8 but silently drops to x1, or chased a completion timeout in a root complex, you already know the behaviour lives in the protocol stack. Understanding the three layers — and the precise job each one owns — is what separates guesswork from systematic debug. This article walks the stack top to bottom, following a single memory read from an endpoint's software driver down to the wire and back.
The layered model, and why PCIe is split this way
PCIe deliberately mirrors a networking stack. Each layer has a narrow contract with the layer above and below, so a change in SerDes technology (Gen3 8 GT/s vs Gen5 32 GT/s) does not force a rewrite of transaction routing. The three device layers are the Transaction Layer, the Data Link Layer, and the Physical Layer. Above them sits the device's own software/configuration model; below them is the physical medium of differential pairs.
Transaction Layer: building the packet
The Transaction Layer is where intent becomes a packet. When a driver issues a 64-byte memory read, the Transaction Layer assembles a Transaction Layer Packet (TLP): a header (3 or 4 double-words), optional data payload, and an optional end-to-end CRC (ECRC). The header encodes the type (MRd, MWr, CfgRd, Completion), the address, the requester ID, a tag, and traffic-class/attribute bits.
Crucially, PCIe uses split transactions: a read request and its completion are separate TLPs. The requester fires a Memory Read, then waits; the completer later returns one or more Completion-with-Data (CplD) TLPs. This is why a stalled completer shows up as a "completion timeout," not a hung bus.
This layer also owns credit-based flow control. Before a TLP is sent, the transmitter checks it has enough posted/non-posted/completion credits advertised by the receiver's buffers. No credits, no transmit — which prevents receiver overrun without any retries. In a protocol analyzer like a Teledyne LeCroy Summit or a Keysight exerciser, you watch these credits tick down and refill via UpdateFC DLLPs.
Key fact: A single Gen3 x16 link carries ~15.75 GB/s usable after 128b/130b overhead. Headers, flow-control credits and small payloads easily cut effective throughput in half, so max-payload-size (MPS, 128B–4096B) is one of the most impactful tunables for real bandwidth.
Data Link Layer: making delivery reliable
The Transaction Layer assumes a reliable pipe — the Data Link Layer (DLL) provides it. On transmit, the DLL prepends a 12-bit sequence number to each TLP and appends a 32-bit LCRC, then stores a copy in its replay buffer. On the receiver, the DLL checks the LCRC and sequence order. A good TLP earns an ACK DLLP; a corrupt or out-of-order one earns a NAK, triggering the transmitter to replay every TLP from its buffer since the last ACK.
The DLL also generates its own Data Link Layer Packets (DLLPs) — ACK/NAK, flow-control updates, and power-management messages. DLLPs never leave the link; they are strictly point-to-point. The DLL is what brings the link from the physical "up" state into DL_Active, the condition the Transaction Layer needs before it will send a single TLP.
Physical Layer: putting bits on the wire
The Physical Layer (PHY) is split into a logical sub-block and an electrical sub-block. The logical PHY frames packets, scrambles the data stream (to spread spectral energy and reduce EMI), applies the line code, and stripes bytes across the available lanes. PCIe Gen1/Gen2 use 8b/10b encoding (25% overhead); Gen3 onward switched to the far leaner 128b/130b. The electrical sub-block drives the actual low-voltage differential pairs, with no separate clock wire — the clock is embedded and recovered by the receiver's CDR.
Before any data flows, the PHY runs Link Training and Status State Machine (LTSSM): Detect → Polling → Configuration → L0. This is where lane count and speed are negotiated, lane-to-lane skew is de-skewed, and equalization is tuned. A board layout fault or marginal channel usually manifests here — a link that trains to x1 instead of x4, or drops from Gen4 to Gen2. Tools like Synopsys HSPICE, Cadence Sigrity and Siemens HyperLynx are used to simulate the channel and eye diagram long before silicon exists.
Key fact: At Gen5 (32 GT/s), unit intervals shrink to ~31 ps. At those speeds the channel budget is so tight that transmitter equalization (preset negotiation during LTSSM Recovery) and receiver CTLE/DFE are mandatory, not optional — which is why signal-integrity sign-off has become inseparable from protocol verification.
Following one read, end to end
| Step | Layer | What happens |
|---|---|---|
| 1 | Transaction | Driver read → MRd TLP built, tag assigned, non-posted credit checked |
| 2 | Data Link | Sequence number + LCRC added, copy stored in replay buffer |
| 3 | Physical | Scramble, 128b/130b encode, stripe across lanes, serialize |
| 4 | Physical (RX) | CDR recovers clock, de-skew lanes, decode, de-scramble |
| 5 | Data Link (RX) | LCRC + sequence check → ACK returned to requester |
| 6 | Transaction (RX) | Completer reads memory, builds CplD TLP; the whole stack repeats in reverse |
Seeing the request and completion as distinct journeys through all three layers is the mental model that makes PCIe debug tractable. For a deeper dive into the electrical and training mechanics alone, see our companion piece on the PCIe physical layer and link training, and for the packet formats themselves, our PCIe TLP packet format reference.
Ready to work through real TLP captures and LTSSM states hands-on? Our PCIe & high-speed protocols course on CourseTron takes you from first principles to analyzer-driven debug. Teams needing silicon-level PCIe IP verification can also talk to the design engineers at Avecas VLSI design services.
Frequently asked questions
What is the difference between a TLP and a DLLP?
A TLP (Transaction Layer Packet) carries end-to-end information — memory/IO/config requests and completions — and is routed across switches. A DLLP (Data Link Layer Packet) is strictly link-local: ACK/NAK, flow-control credit updates and power management. DLLPs never traverse a switch.
Why does PCIe use split transactions?
Because a read's latency to memory is unpredictable. Decoupling the request from its completion lets the link carry other traffic while the completer fetches data, maximizing utilization. The cost is bookkeeping: tags, flow-control credits and completion timeouts.
What does the ACK/NAK mechanism actually protect against?
Transient bit errors on the physical channel. The LCRC catches corruption, the sequence number catches dropped or reordered TLPs, and the replay buffer lets the transmitter resend without the Transaction Layer ever knowing an error occurred.
At what layer is link speed and width negotiated?
The Physical Layer, via the LTSSM state machine during training (Polling and Configuration states), before the Data Link Layer reaches DL_Active or any TLP is exchanged.