APB protocol

In short: The apb protocol (Advanced Peripheral Bus) is the low-power, low-bandwidth member of the AMBA family, built for simple register-mapped peripherals like timers, GPIO and UART. Every transfer takes a fixed two-cycle shape — a Setup phase followed by an Access phase — and there are no bursts, no pipelining and no out-of-order traffic, which is exactly why it is so easy to design and verify.

What Is apb protocol?

The apb protocol is a synchronous, unpipelined bus defined by Arm as part of the AMBA (Advanced Microcontroller Bus Architecture) specification. It connects a single bus bridge — the APB Requester, historically called the master — to one or more peripheral Completers (slaves). Its whole reason to exist is to keep slow, infrequently accessed peripherals off the high-speed system interconnect so they do not complicate or slow down the main CPU-to-memory path.

In a typical system-on-chip, a fast bus such as AXI or AHB carries the heavy traffic between the processor, caches and DRAM controller. A bridge sits on that fast bus and translates the occasional “write 0x1 to the UART control register” request into a clean, simple APB transaction. Because APB targets are things that change state rarely, the bus trades throughput for simplicity, small gate count and low power.

The Signals You Actually Need

APB keeps its signal list deliberately short. The core signals are driven by the Requester unless noted:

• PCLK — the bus clock; everything is sampled on its rising edge.
• PRESETn — active-low reset, usually shared with the system reset.
• PADDR — the peripheral address bus.
• PSELx — a per-Completer select line; asserted to pick which peripheral is addressed.
• PENABLE — marks the second (Access) cycle of a transfer.
• PWRITE — high for a write, low for a read.
• PWDATA / PRDATA — write and read data buses.
• PREADY — driven by the Completer to extend a transfer with wait states.
• PSLVERR — optional error flag from the Completer.

Notice there is no burst-length signal, no ID tag and no separate response channel. A transfer is addressed, data moves, and it is done.

Setup and Access: The Two Phases

Every APB transaction walks through the same tiny state machine with three states: IDLE, SETUP and ACCESS.

1. IDLE — the default. No PSEL is asserted and the bus is quiet.
2. SETUP phase — the Requester drives PADDR, PWRITE, PWDATA (for a write) and asserts the appropriate PSELx, but keeps PENABLE low. The bus always spends exactly one clock here.
3. ACCESS phase — on the next rising edge the Requester asserts PENABLE high, holding all the other signals stable. The Completer samples the address and data (for a write) or presents PRDATA (for a read). The transfer completes when PREADY is high on a clock edge while PENABLE is high.

If the Completer needs more time, it simply holds PREADY low; the bus stays in the ACCESS state, stretching the transfer by wait states. When PREADY finally goes high the transfer ends, and the bus either returns to IDLE or, if another access is pending, goes straight back to SETUP.

Why There Are No Bursts

High-performance buses amortize address overhead by sending one address and then streaming many data beats — a burst. APB deliberately refuses this. Each access carries its own address, and a new transfer cannot overlap with the previous one. There is no pipelining of the address phase into the data phase of the next transaction either.

This sounds wasteful, and for bulk data it would be. But APB peripherals are register files, not memories. You write a baud-rate register, set an interrupt mask, read a status flag. These are single, scattered 32-bit accesses where simplicity and tiny silicon area matter far more than peak bandwidth. Dropping bursts removes an enormous amount of logic from both the Requester and every Completer, and it makes formal verification almost trivial because the protocol has so few legal states.

APB and Power

Because signals only toggle during an active transfer and the bus sits in IDLE the rest of the time, APB switching activity is naturally low. There is no speculative prefetch, no outstanding-transaction bookkeeping and no clock-hungry arbitration fabric between multiple masters — APB has a single Requester. For battery-powered microcontrollers this low dynamic power is a major reason the peripheral subsystem lives on APB.

How APB Fits With AHB and AXI

The three buses form a performance hierarchy. AXI offers independent read/write channels, long bursts and many outstanding transactions for the CPU and memory. AHB is a pipelined single-channel bus for medium-speed traffic. APB sits at the bottom for the slow stuff. A system usually has an AXI-or-AHB-to-APB bridge that absorbs the complexity so peripherals only ever see clean two-phase transfers. That layering lets designers reuse the same tiny APB peripheral IP across many chips regardless of the fast bus above it.

apb protocol — FAQ

Is APB a master-slave or requester-completer bus?

Both terms describe the same roles. Older AMBA documents use master/slave; newer revisions use Requester (the bridge driving transfers) and Completer (the addressed peripheral). APB allows only one Requester on the bus.

How many clock cycles does one APB transfer take?

A minimum of two: one Setup cycle and one Access cycle. If the Completer drives PREADY low, the Access phase is extended by one cycle per wait state, so a transfer with N wait states takes 2 + N cycles.

Does APB support error responses?

Yes, optionally. A Completer can assert PSLVERR during the Access phase to signal that the transfer failed — for example an access to an unmapped register. If a peripheral never needs to report errors, it can simply tie PSLVERR low.

Why use APB instead of just putting everything on AXI?

APB peripherals are far smaller and lower power because they skip bursts, pipelining, multiple IDs and arbitration. Putting a simple GPIO block directly on AXI would add logic and power for throughput it will never use, so the bridge-plus-APB approach is cheaper overall.

Related: AXI vs AHB vs APB · Glossary · all courses.