In short: AMBA AXI is a high-performance, point-to-point SoC interconnect protocol that splits every transaction into five independent channels tied together by a universal VALID/READY handshake, letting masters and slaves pipeline and reorder bursts for maximum throughput.
Open the floorplan of any modern application processor, GPU, or AI accelerator and you will find the same connective tissue binding the CPU clusters, DRAM controllers, and accelerators together: ARM's Advanced eXtensible Interface (AXI), part of the AMBA family. Since AXI4 arrived with AMBA 4 in 2010, it has become the default load-bearing bus for performance-critical on-chip traffic. Understanding its channel structure and handshake is non-negotiable for anyone working in SoC integration, RTL design, or design verification.
Why five channels instead of one bus?
Older AMBA buses such as APB and the original AHB bundled address and data onto a shared, mostly sequential path. AXI breaks a transaction into five independent channels, each with its own handshake and its own direction of flow. The read side uses two channels; the write side uses three.
- AR — Read Address: master drives address, burst length, size, ID.
- R — Read Data: slave returns data beats plus a response code.
- AW — Write Address: master drives the write address and burst attributes.
- W — Write Data: master streams the data beats, with byte-lane strobes (WSTRB).
- B — Write Response: slave acknowledges that the whole write burst committed.
Because the channels are decoupled, a master can issue a read address on AR and immediately follow with a write address on AW in the same cycle, while read data from a previous request is still arriving on R. This concurrency is the whole point: it is what lets a DDR controller keep hundreds of nanoseconds of DRAM latency hidden behind a continuous stream of outstanding requests.
Address and data are separated: a master can send an address and then wait many cycles for data without stalling the address channel for other transactions. This is why AXI is called a split-transaction protocol.
The VALID/READY handshake
Every one of the five channels moves information with exactly the same two-wire handshake, which is the single most important idea to internalise. The source asserts VALID when it has placed stable payload on the bus; the destination asserts READY when it can accept it. Transfer happens on the rising clock edge where both VALID and READY are high.
The protocol imposes one strict rule that catches out many engineers: once a source asserts VALID, it must keep VALID high and must not change the payload until the handshake completes. The destination, however, may assert or deassert READY freely. A source must never wait for READY before asserting VALID — that creates a deadlock where each side waits for the other. We cover the subtle timing cases of this in our companion piece on the AXI handshake in depth.
The burst model
AXI is burst-based. A single address phase describes a burst of up to 256 data beats (AXI4; the earlier AXI3 capped at 16). The master specifies three fields that fully define the burst geometry: AxLEN (beats minus one), AxSIZE (bytes per beat, up to the full bus width), and AxBURST (the addressing mode).
| Burst type | Address behaviour | Typical use |
|---|---|---|
| FIXED | Same address every beat | FIFO / peripheral register |
| INCR | Address increments by AxSIZE | Cache line, memcpy, DMA |
| WRAP | Increments then wraps at a boundary | Critical-word-first cache refill |
A concrete example: a 64-bit (8-byte) AXI bus serving a 64-byte cache line issues an INCR burst with AxSIZE=3 (8 bytes) and AxLEN=7 (8 beats). 8 beats × 8 bytes = 64 bytes in a single address transaction. A key constraint drilled into every verification plan: an AXI burst must not cross a 4 KB address boundary, because 4 KB is the smallest page granularity and a burst must stay within one slave's decode region.
Transaction IDs (AWID/ARID) let a master have many outstanding transactions. Responses sharing an ID must return in order; responses with different IDs may be reordered by the slave for efficiency. This is how out-of-order memory systems boost DRAM row-buffer hit rates.
Responses, strobes, and QoS
Each read beat (RRESP) and each write burst (BRESP) carries a 2-bit response: OKAY, EXOKAY (exclusive access success), SLVERR (the slave reached but errored), or DECERR (no slave decoded — usually a bad address). Treating SLVERR and DECERR correctly is a frequent source of real silicon bugs. On the write data channel, WSTRB byte strobes let a master write only selected bytes within a beat, which is essential for sub-word stores and unaligned accesses.
Verification and tooling
Because the handshake rules are strict but the channels are concurrent, AXI is verified almost entirely with assertion-based methodologies. Commercial VIP (Verification IP) from Synopsys VC VIP, Cadence, and Siemens EDA (Questa/UVM) ships pre-written SystemVerilog Assertions that flag protocol violations — a dropped VALID, a changed payload mid-handshake, or a 4 KB crossing — the moment they occur in simulation. In our hands-on labs we drive AXI VIP under Synopsys VCS and Siemens Questa and inspect waveforms in Verdi. Teams building custom AXI fabrics for tapeout often lean on specialist SoC design-services partners like Avecas for fabric integration and timing closure.
Ready to build and verify a real AXI interconnect in UVM? Our SoC Protocols & Verification track walks you from handshake to full crossbar — see the AXI crossbar interconnect guide next.
Frequently asked questions
What is the difference between AXI4 and AXI4-Lite?
AXI4-Lite is a simplified subset for low-throughput control registers: it supports only single (non-burst) transfers, a fixed data width of 32 or 64 bits, and no transaction IDs. Full AXI4 adds bursts up to 256 beats and out-of-order IDs.
Can a master change the address after asserting VALID?
No. Once VALID is asserted on any channel, every payload signal must stay stable until READY is also high and the transfer completes. Changing it is a protocol violation that VIP will flag immediately.
Why can't an AXI burst cross a 4 KB boundary?
4 KB is the minimum memory page size, and the address decode that routes a burst to a slave operates at page granularity. A burst crossing 4 KB could target two different slaves, which the single-address-phase model cannot express.
How is AXI different from AXI-Stream?
AXI-Stream (AXIS) is address-less and unidirectional — pure data flow for streaming blocks like DSP pipelines. Full AXI is memory-mapped with read/write addresses and responses.