In short: The ahb protocol (Advanced High-performance Bus) is AMBA's backbone for connecting fast on-chip masters like a CPU or DMA to high-bandwidth slaves such as memory controllers. It uses a pipelined address/data phase, burst transfers, and a central arbiter so one master drives the bus at a time while throughput stays high.
The ahb protocol is a synchronous, high-bandwidth bus defined by Arm as part of the AMBA (Advanced Microcontroller Bus Architecture) family. It sits at the top tier of a typical SoC, joining the elements that need serious throughput: the processor, a DMA controller, an on-chip SRAM, an external memory interface, and a bridge down to the slower APB peripheral bus.
AHB is built around three roles. A master initiates reads and writes. A slave responds to the transfer addressed to it. An arbiter decides which master owns the bus in any given cycle, and a decoder selects the target slave from the address. Everything is clocked on the rising edge of a single bus clock (HCLK), which makes the timing simple to reason about and easy to synthesise.
Because several masters may want the bus at once, AHB centralises control in an arbiter. A master asserts HBUSREQ, the arbiter grants it with HGRANT, and only the granted master drives HADDR, HWRITE, HSIZE, HBURST and HTRANS. The addressed slave answers on HRDATA (reads) or latches HWDATA (writes) and reports status on HRESP.
This single-master-per-cycle rule keeps the shared wires free of contention, while arbitration schemes (round-robin, priority, or fair) decide fairness between masters. A master can also signal HLOCK to hold the bus across a locked sequence, which matters for atomic read-modify-write operations.
The defining feature of AHB is its two-stage pipeline. Every transfer has an address phase (one cycle, where the master presents the address and control) and a data phase (one or more cycles, where data moves and the slave may insert wait states via HREADY). Crucially, the address phase of transfer N+1 overlaps the data phase of transfer N. The bus therefore pipelines back-to-back accesses rather than waiting a full round trip for each.
Slaves use HREADY to stretch the data phase: driving it low inserts wait states, which stalls the whole pipeline cleanly without corrupting pending addresses. The master watches HRESP for an OKAY, ERROR, RETRY or SPLIT response and reacts accordingly.
Rather than issuing one address per word, AHB lets a master declare a burst up front with HBURST. The arbiter and slave then know a run of related accesses is coming, which improves memory efficiency and reduces re-arbitration. Common burst types include:
The HTRANS signal classifies each beat as IDLE, BUSY, NONSEQ (first beat of a burst) or SEQ (subsequent beats), so the slave always knows exactly where it is in the sequence.
The original AHB supports multiple masters with full arbitration and SPLIT/RETRY responses. AHB-Lite is a simplified single-master variant that drops arbitration and the SPLIT mechanism; it is extremely common because many designs route a single master (often a bus matrix port) to a set of slaves. Above AHB sits AXI for independent, out-of-order, multi-channel transactions; below it sits APB for simple, low-power peripheral registers reached through a bridge.
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Explore CourseTron Courses →AHB is fully synchronous. All transfers are timed to the rising edge of a single bus clock, HCLK, which keeps timing closure and verification straightforward.
Only one at a time. The arbiter grants bus ownership to a single master per cycle; other masters wait their turn even though the pipeline keeps overall throughput high.
AHB-Lite is a reduced single-master version that removes arbitration signals and the SPLIT/RETRY responses. Full AHB keeps multi-master arbitration, making it heavier but more flexible.
HREADY lets a slave insert wait states to stretch the data phase when it needs more time, pausing the pipeline safely without losing the addresses already issued.
Related: AXI vs AHB vs APB · Glossary · all courses.