FPGA clock management (MMCM/PLL)

In short: An MMCM (or PLL) is a feedback-controlled clock synthesizer inside the FPGA that takes one input clock and produces several phase-aligned, frequency-scaled, jitter-filtered output clocks you cannot build safely with logic or dividers alone.

Almost every non-trivial FPGA design needs more than the one clock arriving at a pin. A video pipeline wants 148.5 MHz for the pixel stream and a 5× serial clock for the transmitter; a DDR controller wants a clock plus a 90°-shifted copy to center the strobe in the data eye; a processor fabric wants 100 MHz from a 25 MHz oscillator. You could divide a clock with a counter, but that produces a glitchy, duty-cycle-skewed, high-jitter signal routed on ordinary fabric. The right tool is the dedicated clock-management block: on AMD/Xilinx parts the MMCM (Mixed-Mode Clock Manager) and the simpler PLL; on Intel/Altera parts the fabric PLL. This article explains what they actually do and how to drive them without shooting yourself in the foot at timing closure.

Why a counter is not a clock synthesizer

A ripple counter dividing by N gives you f/N, but nothing else you want. You cannot get a frequency higher than the input, you cannot get a non-integer ratio like 5/2, the output toggles on the fabric clock network with large insertion delay, and the phase relationship to the source drifts with temperature and voltage. An MMCM instead builds a phase-locked loop: a phase-frequency detector compares the divided feedback clock against the divided input, a charge pump and loop filter steer a voltage-controlled oscillator (VCO), and the loop settles when the two match. Once locked, the VCO runs at a clean, high frequency from which the output counters derive every requested clock in exact phase.

The frequency equation you must satisfy

Every output frequency follows one formula:

f_VCO = f_CLKIN × M / D  and  f_OUTn = f_VCO / O_n

The catch is that f_VCO must land inside the device's VCO range — for example roughly 600–1600 MHz on a 7-series MMCM (speed-grade dependent). So to make 100 MHz and a 500 MHz serial clock from a 50 MHz input, you pick M=20, D=1 to get a 1000 MHz VCO, then O=10 for 100 MHz and O=2 for 500 MHz. The tools (Vivado's Clocking Wizard, Quartus's IP Catalog PLL) solve this for you, but understanding the constraint explains why some frequency combinations are rejected: they have no common VCO.

Key fact: A single MMCM has one VCO, so all of its output clocks are integer-divided from the same VCO frequency. If two required clocks share no integer-divisible common multiple inside the legal VCO band, you need a second clocking primitive.

Phase shifting: static and dynamic

Because each output counter can start on a chosen VCO edge and the MMCM has a fine phase interpolator, you can request outputs shifted by a fixed amount — 90°, 45°, or an arbitrary value — at build time. This is how DDR interfaces place the capture clock in the middle of the read data window, and how you de-skew a forwarded source-synchronous clock. For runtime adjustment, the MMCM's dynamic phase shift port steps the output phase in fine increments (1/56 of the VCO period on 7-series), which calibration logic uses to sweep the data eye and lock onto the best sampling point. The simpler PLL primitive supports coarse fixed phase but not the fine dynamic shift — a common reason designers choose the MMCM over the PLL.

Jitter: filtering versus generating

A PLL is a low-pass filter for phase. Input jitter faster than the loop bandwidth is attenuated; jitter slower than the bandwidth passes through. This is genuinely useful: a noisy board oscillator can be cleaned up by a narrow loop. But the loop also adds its own jitter from the VCO and charge pump, so there is an optimum bandwidth. Vivado reports two numbers worth reading in every report: the output's period jitter and the phase error, both of which the static timing analysis folds into your setup/hold margins automatically. If you cascade an MMCM into a second MMCM you multiply the jitter contributions — avoid cascading unless the frequency plan forces it.

Key fact: Period jitter from the MMCM is not free — it is subtracted from your timing budget. On a 500 MHz clock (2 ns period), a few hundred picoseconds of jitter is a double-digit percentage of the whole budget, so clock-plan choices directly change whether a design closes timing.

Where the output goes next

An MMCM output is not yet a usable clock network — it must drive a global buffer (BUFG) to reach the fabric's low-skew spine, and it is physically tied to a specific clock region. Getting the region and buffer placement right is a whole topic of its own; see our companion piece on clock regions and BUFG routing, and, for the downstream consequences of crossing between these generated domains, our guide to clock domain crossing (CDC). Treating the MMCM output as if it were an ordinary signal — gating it in logic, routing it off the clock network — is the single most common beginner mistake and produces designs that appear to work on the bench and fail in the field.

Animated view: multiply and phase-shift in action

MMCM versus PLL: which to reach for

Rule of thumb: if you only need a couple of integer-related clocks from one source, use the PLL and save the MMCM for the interface that actually needs its phase controls. Teams building production interfaces — and the sign-off methodologies around Synopsys PrimeTime, Cadence Tempus and Siemens Questa that verify them — treat the clock plan as an architectural decision made before RTL, not a wizard clicked at the end.

Want to design clock trees that close timing the first time? Our FPGA track walks through MMCM/PLL planning, CDC, and timing closure with real boards — browse the CourseTron FPGA courses. For a deeper ASIC-side perspective on clocking and sign-off, our design-services partner Avecas VLSI design services works these flows on tapeout-grade silicon.

Frequently asked questions

Can I generate a clock faster than my input oscillator?

Yes. That is the whole point of the M multiplier: a 25 MHz crystal feeding M=40, D=1 produces a 1000 MHz VCO, from which you can derive outputs well above the input. The only limit is the VCO band and the output counter's minimum divide.

Why does my design work until I slightly change a clock frequency?

Changing one output frequency can force the tool to pick a different VCO, which changes the divide of every other output and can push a frequency combination out of the legal band or worsen jitter. Always re-check the Clocking Wizard's reported VCO and jitter after any change.

Do I need an MMCM just to invert or divide a clock by two?

For a simple /2 you can often use a BUFGCE_DIV or a clock-enable scheme rather than burning an MMCM, which avoids added jitter and lock time. Reserve the MMCM for cases that need multiplication, non-integer ratios, or phase control.

How long does an MMCM take to lock?

Typically tens to hundreds of microseconds after the input clock is stable. Your reset logic must hold downstream fabric in reset until the MMCM's LOCKED output asserts, or the first clock edges will be unreliable.