In short: FPGA clocks travel on a dedicated low-skew tree built from global buffers (BUFG) that drive clock regions across the die, and choosing the right buffer — global BUFG, regional BUFR/BUFH, or multi-region BUFMR — is what keeps millions of flip-flops sampling within the same few-hundred-picosecond window.
Ask any FPGA timing engineer what separates a design that closes at 400 MHz from one that fails routing, and the answer is rarely the logic. It is almost always the clock. Unlike an ASIC, where the clock tree is synthesized cell-by-cell during place-and-route, an FPGA ships with a pre-built clock distribution fabric. Your job is to steer signals onto it correctly. This article explains how that fabric is organized into clock regions, what BUFG and its siblings actually do, and how skew is controlled across a device that can be 20+ mm on a side.
Why a dedicated clock network exists
A clock is the one net in your design that must reach tens of thousands of endpoints with nearly identical arrival time. If you routed it on ordinary signal interconnect, the RC delay would vary wildly between a nearby flip-flop and one on the far corner, producing skew of several nanoseconds — enough to break hold timing everywhere. Instead, FPGA vendors pre-fabricate balanced, low-resistance metal spines with built-in buffers.
On a modern 16 nm device, the global clock backbone delivers skew on the order of 100–300 ps edge-to-edge across the whole die, versus the 2–5 ns you would see on general routing — a 10–20× improvement that is simply unavailable to normal nets.
Clock regions: slicing the die
Vendors partition the device into a grid of clock regions (Xilinx uses this exact term; Intel/Altera calls the equivalent areas clock sectors). On a Xilinx UltraScale+ part, each clock region is a fixed rectangle — roughly 60 CLBs tall and spanning a column of the device — and a large part may contain a 5×8 array of these regions. Each region has its own set of horizontal and vertical clock routing tracks and a bank of leaf clock buffers that drive the flip-flops, BRAM, and DSP inside it.
The key architectural idea is a two-tier hierarchy: a global network carries a clock to the boundary of every region, and local leaf distribution fans it out to endpoints inside the region. This mirrors an H-tree, but it is laid out as a horizontal spine feeding vertical branches per region.
The buffer family: BUFG and its relatives
A BUFG (Global Clock Buffer) is the on-ramp to the global network. It is a dedicated hard primitive — not built from LUTs — sitting between a clock source (an input buffer, an MMCM/PLL output, or GT recovered clock) and the global spine. Only a BUFG output may legally drive the global clock tracks, which is why synthesis tools (Vivado, Quartus) automatically insert one whenever a signal fans out to many sequential elements. The relatives trade reach for count and latency:
| Buffer | Scope | Typical use |
|---|---|---|
| BUFG / BUFGCE | Entire device (all regions) | System clocks; BUFGCE adds a glitch-free clock enable |
| BUFGMUX | Device-wide, 2-input | Glitchless switch between two clock sources |
| BUFH / BUFGCE_DIV | One clock region (horizontal) | Low-skew local clock, frees a scarce global |
| BUFR | One region, with ÷1–8 divider | Source-synchronous receive logic |
| BUFMR | Multi-region (adjacent) | Fan a BUFR/BUFIO clock across stacked regions |
| BUFIO | I/O column only | Highest-speed clock for ISERDES/OSERDES |
Global clock resources are finite — a UltraScale+ device offers 24 BUFGCEs per clock region but the global spine capacity is what gets exhausted first. A common "too many clocks" routing failure is really a shortage of global tracks, fixed by demoting non-critical clocks to regional BUFH/BUFR buffers.
Skew, and why the clock enable matters
Skew is the difference in clock arrival time between any two endpoints. Because the global tree is balanced by construction, the dominant skew contributor in practice is not the tree itself but crossing between clock domains or networks. A classic mistake is gating a clock with a LUT-based AND gate to "save power": the gate sits on general routing, adds variable delay, and injects skew and glitches. The correct approach is the enable pin of BUFGCE, or the CE input of the flip-flop. We cover that trade-off in depth in our companion piece on gated clocks in FPGA designs.
When you genuinely need two related clocks phase-aligned — say a 200 MHz logic clock and a 200 MHz I/O clock — you drive both from the same MMCM and let its feedback loop compensate the BUFG insertion delay. This is the same deskew principle an ASIC flow (Synopsys ICC2, Cadence Innovus) achieves with clock-tree synthesis, except the FPGA MMCM does it dynamically with a phase detector. For the mechanics of phase relationships and crossing them safely, see our note on clock domain crossing basics.
Animated: an edge propagating down the tree
A worked placement example
Suppose a video pipeline uses a 148.5 MHz pixel clock (HDMI), a 200 MHz AXI clock, and a 74.25 MHz divided clock for a downstream block. Three device-wide BUFGs would work, but if the pixel logic is confined to two adjacent clock regions near the I/O bank, you can drive it from a BUFMR fed by a BUFR divider, reserving the scarce global tracks for the AXI clock that truly spans the chip. Vivado's clock utilization report (report_clock_utilization) shows exactly how many global and regional resources each net consumes — reading it is a core skill we drill in the lab.
Common failure modes
- Clock on local routing: a clock net that misses a BUFG routes on general interconnect — placement-dependent skew, intermittent timing failures. Vivado warns with a
CLOCK_DEDICATED_ROUTEerror. - Region overflow: loads spread beyond a BUFR/BUFH's single region, forcing an illegal cross-region leaf route.
- Too many globals: more high-fanout clocks than global tracks; demote some to regional buffers.
- Unconstrained generated clocks: divided clocks without a
create_generated_clockconstraint get analyzed against the wrong period.
Teams building production FPGA logic or migrating RTL to silicon often lean on specialist help; our design-services partner Avecas VLSI design services handles exactly these clock-architecture decisions on customer boards.
Want to master FPGA clocking hands-on — BUFG selection, MMCM deskew, and timing closure in Vivado? Explore the FPGA track in our CourseTron course catalog.
FAQ
What is the difference between BUFG and BUFH?
BUFG drives the device-wide global clock network and reaches every clock region; BUFH drives only the horizontal clock spine of a single region. BUFH conserves scarce global resources when a clock's loads are confined to one region, at the cost of not reaching the rest of the die.
How many global clocks can an FPGA have?
It depends on the family. A Xilinx UltraScale+ device provides up to 24 BUFGCE sites per clock region, but the global routing backbone limits how many high-fanout clocks can span the whole chip simultaneously — typically on the order of 16–32 truly global clocks, which is why demoting non-critical clocks to regional buffers is a standard timing-closure tactic.
Does an FPGA do clock-tree synthesis like an ASIC?
No. The low-skew tree is pre-fabricated in silicon, so there is no per-design CTS step as in Synopsys ICC2 or Cadence Innovus. You instead choose the correct buffer primitive and use MMCM/PLL feedback to compensate insertion delay and align related clocks.
Why does Vivado insert a BUFG automatically?
Any net that fans out to a large number of sequential elements is recognized as a clock, and only a BUFG output may legally drive the global clock tracks. Synthesis inserts the buffer so the clock uses the dedicated low-skew network rather than general routing.