Lookup Table in FPGA

In short: A k-input LUT is a tiny 2^k-bit SRAM whose stored bits are the truth table, read out through a multiplexer tree steered by the inputs, so it can implement any Boolean function of k variables, and a slice pairs each LUT with a flip-flop so the same cell can be either combinational logic or a registered stage.

Why an FPGA stores truth tables instead of gates

A fixed-function chip wires AND, OR and XOR gates together at fabrication time. An FPGA cannot do that, because the same silicon must become a UART today and an image filter tomorrow. The trick is to stop thinking of logic as gates and think of it as memory. Any combinational function of k inputs is fully described by its truth table, which has 2^k rows, and each row is a single output bit. Store those bits in SRAM, use the inputs as an address, and the memory returns the answer. That is a lookup table.

The cost of this generality grows fast: a 4-input LUT needs 16 SRAM bits, a 6-input LUT needs 64. Modern Xilinx and Intel fabrics settled on 6 inputs (Xilinx 6-LUT, Intel ALM with 8 inputs split flexibly) because beyond that the memory doubles with every extra input while the average logic function does not use the extra inputs. For a broader tour of where the LUT sits in the device, see our guide to FPGA architecture.

Anatomy of a k-input LUT

Physically a LUT has two halves. The first is the configuration memory: 2^k SRAM cells loaded from the bitstream when the device powers up. The second is a multiplexer tree: the k inputs act as select lines, and each level of the tree halves the number of candidate bits until one remains. A 2-input LUT needs three 2:1 muxes, a 4-input LUT needs fifteen, and a 6-input LUT needs sixty-three, though real silicon shares pass-transistor stages to save area and uses the first-level inputs for the fastest paths.

Key fact: Changing the function never changes the wires. Turning an AND into an XOR means rewriting the 2^k SRAM bits, nothing else. That is why a bitstream reload reconfigures the whole device.

Worked example: a 4-input function

Take Y = (A AND B) OR (C XOR D). The truth table has 16 rows. Rows where C and D differ output 1 regardless of A and B. Rows where C equals D output 1 only if A and B are both 1. Count the ones: for CD = 01 or 10 there are 4 rows each (all A, B), giving 8 ones, and for CD = 00 or 11 only AB = 11 qualifies, giving 2 more, so 10 ones in total. Synthesis tools such as Synopsys Synplify, Vivado synthesis or Intel Quartus compute this 16-bit INIT value automatically; in Xilinx netlists you will see it as a hex string such as INIT=16'hFEE8 style attribute on a LUT4 primitive.

(* keep *) LUT4 #(.INIT(16'hFEE8)) u_f (.I0(a), .I1(b), .I2(c), .I3(d), .O(y));

The constant is just the truth table read from row 15 down to row 0. Nothing about the logic depth matters: a simple inverter and a monster parity function cost the same single LUT, and both have the same delay through the cell.

Watching a bit travel through the mux tree

The slice: LUT plus flip-flop

A LUT alone is purely combinational. To build state machines, counters and pipelines, each LUT output can feed a flip-flop in the same slice. A Xilinx 7-series slice, for example, holds four 6-input LUTs and eight flip-flops, plus carry logic (CARRY4) and wide multiplexers (F7/F8) that combine LUT outputs into 7- and 8-input functions. A configuration bit chooses whether the slice output comes directly from the LUT or from the flip-flop.

Key fact: Using the flip-flop that already sits beside the LUT is free. Putting a register after every few LUTs costs almost no area, which is why pipelining in FPGA is so effective for raising clock frequency.

LUT as memory and shift register

Because the LUT is literally SRAM, some slices (SLICEM in Xilinx parts) let you write it at run time. One 6-LUT becomes a 64x1 distributed RAM, and a chain of LUTs becomes a shift register up to 32 bits deep per LUT, which you can learn more about in our article on the SRL shift-register LUT. That is far cheaper than 32 flip-flops, though the output tap is read through the LUT rather than being a registered value.

What this means for timing and interviews

Logic delay is counted in LUT levels, not gates. A path of three LUTs plus routing may run at 300 MHz on a mid-range device, while eight levels may struggle past 150 MHz, and routing often costs more than the LUTs themselves. When Vivado or Quartus reports a timing failure, the usual fix is to restructure logic to cut LUT levels, retime across the available flip-flops, or add a pipeline stage. Interviewers commonly ask: how many LUT4s are needed for a 6-input function (answer: at most five using Shannon decomposition, fewer if the function is structured); why LUT size is 4 to 6; and what a flip-flop in the slice buys you. For the full resource picture, read our look-up table primer alongside this piece.

Teams that need production-grade RTL and constraint closure often engage design services such as Avecas, while learners can build the same skills hands-on through ChipXpert training programs.

Ready to design real FPGA logic? Explore the hands-on FPGA modules in our CourseTron courses and build LUT-level designs yourself.

FAQ

How many functions can a 4-input LUT implement?

Each of the 16 truth-table rows can be 0 or 1, so a 4-input LUT can implement 2^16 = 65,536 distinct Boolean functions.

Why not use bigger LUTs, like 10 inputs?

Memory and mux area double with each input, while most real logic needs only a few inputs. Mid-sized LUTs (4 to 6) give the best area and delay trade-off, with wide functions built by combining LUTs.

Is a LUT volatile?

In SRAM-based FPGAs yes: the contents are lost at power-down and reloaded from the bitstream, often stored in external flash. Flash-based FPGAs retain configuration.

Can the flip-flop be used without the LUT?

Yes, a flip-flop can often be fed directly from fabric inputs, bypassing the LUT, though the LUT in that position may then be partly unusable depending on the architecture.