In short: An FPGA look-up table (LUT) is a tiny SRAM that stores the full truth table of a Boolean function, so any K-input combinational logic becomes a single memory read — and the number of inputs K is the knob that trades silicon area, speed, and routing against how much logic each cell can absorb.
Why an FPGA needs LUTs at all
A fixed-function ASIC bakes AND, OR and NOT gates into transistors at the foundry. An FPGA has to implement whatever logic you give it after manufacturing, without re-spinning silicon. The trick is to stop thinking about gates and start thinking about truth tables. Any combinational function of K inputs is completely described by its 2K-row truth table. If you can store that table in memory and address it with the K inputs, you can reproduce any function those inputs allow — no dedicated gate required.
That memory is the look-up table. A K-input LUT is a 2K×1-bit SRAM feeding a 2K-to-1 multiplexer. The K signals drive the mux select lines; the selected SRAM cell drives the output. Program the SRAM differently and the same hardware becomes an AND gate, a 3-input XOR, a carry function, or part of a state-machine decoder.
A K-input LUT holds 2K configuration bits. A 4-LUT stores 16 bits; a 6-LUT stores 64. Those bits are loaded from the bitstream at power-up and are what synthesis tools like AMD Vivado or Intel Quartus actually compute when they "map" your RTL.
How a LUT computes a function: a worked example
Suppose you write y = (a & b) | (~c) in Verilog. Synthesis does not build an AND gate and an OR gate. Instead it enumerates the truth table over inputs {a,b,c} and writes the 8 result bits into one 3-LUT's SRAM:
| c | b | a | SRAM addr | stored bit (y) |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 1 | 1 |
| 0 | 1 | 1 | 3 | 1 |
| 1 | 0 | 0 | 4 | 0 |
| 1 | 1 | 1 | 7 | 1 |
At run time the three inputs form a 3-bit address, one SRAM cell is selected, and its bit appears at the output. Propagation delay is just the mux delay plus the SRAM read — a constant, regardless of whether the function is a trivial buffer or a gnarly 3-variable expression. That constant-delay property is why LUT-based timing is so predictable, and it is the reason FPGA static timing analysis can be done cleanly in tools from the Vivado or Siemens Questa ecosystems.
Watching the LUT in action
The animation below cycles the 3-bit input address and highlights the stored bit being read out — exactly what happens physically as your signals toggle each clock-adjacent region of logic.
Why LUT size drives capacity and speed
If a LUT can swallow any K-input function, why not make K huge? Because cost grows as 2K. Doubling K from 4 to 5 doubles the SRAM bits; a 6-LUT needs 64 cells and a 6-level mux tree. The classic academic result — explored in Rose and Betz's architecture studies — is that logic density per unit area peaks around K = 4 to 6, which is why modern AMD and Intel fabrics standardized on 6-input LUTs, often fracturable into two smaller LUTs sharing inputs.
Bigger LUTs absorb more logic per cell, so a design needs fewer cells and fewer hops through the routing network — the dominant delay in an FPGA. That is the real speed win: not a faster LUT, but fewer slow interconnect segments between LUTs.
| LUT inputs (K) | Config bits | Effect on fabric |
|---|---|---|
| 4 | 16 | Small, area-efficient cell; more cells + more routing per design |
| 6 | 64 | Industry sweet spot; fewer logic levels, shorter critical paths |
| 8+ | 256+ | SRAM/mux cost explodes; most bits wasted on unused functions |
This trade-off is a central theme in our FPGA architecture explained guide, and it connects directly to how tools pack logic into slices — covered in LUTs vs logic elements. For engineers moving from FPGA prototyping into custom silicon, the design-services team at Avecas VLSI design services works these same mapping trade-offs at the ASIC level.
From RTL to LUTs: the synthesis step
When you run synthesis, the tool flattens your RTL into a Boolean network, then performs technology mapping — covering that network with K-feasible cones so each cone fits one LUT. Algorithms in this space (FlowMap and its successors) minimise either LUT count (area) or the number of LUTs on the longest path (depth/delay). The resulting LUT mask bits land in the bitstream. A single 6-LUT can hold, for example, a full 6:1 address decode bit, a one-bit adder's sum, or a slice of a priority encoder — whatever the mapper decides is cheapest.
Want to go from "I can read a truth table" to confidently mapping real RTL onto FPGA fabric? The CourseTron FPGA & Digital Design track walks through LUTs, carry chains, timing closure and hands-on Vivado/Quartus labs.
Frequently asked questions
Is a LUT the same as a logic gate?
No. A gate implements one fixed function; a LUT is reconfigurable memory that can implement any function of its K inputs by changing the stored bits. One LUT often replaces several gates' worth of logic.
Why do most FPGAs use 6-input LUTs?
Architecture studies showed logic density and speed are best balanced around K = 4–6. Six-input LUTs reduce the number of logic levels on critical paths while keeping SRAM cost (64 bits) manageable, so AMD and Intel converged on them, often as fracturable dual-output cells.
How are the LUT contents set?
They are configuration SRAM bits loaded from the FPGA bitstream at power-up. Because it is SRAM, the function is volatile and is re-loaded every time the device is configured.
Can a LUT implement sequential logic?
The LUT itself is purely combinational. Flip-flops sit next to it inside the logic cell; the LUT computes next-state/output logic and the adjacent register stores state on the clock edge.