In short: SPI's four modes (0–3) are just the two-bit combination of clock polarity (CPOL — idle level of SCLK) and clock phase (CPHA — whether data is sampled on the first or second clock edge), and a link only works when master and slave agree on both bits.
The Serial Peripheral Interface looks deceptively simple: four wires, a shift register at each end, and a clock. Yet a large share of "my SPI isn't working" bench sessions trace back to a single culprit — a mode mismatch. Two bits, CPOL and CPHA, decide exactly when each side drives and samples the line, and getting them wrong gives you garbage that almost looks right. This article explains what those two bits physically do, how the four modes map to real sampling edges, and how to match a master to a stubborn datasheet.
Why clock polarity and phase exist at all
SPI is a synchronous, full-duplex protocol. On every clock edge, one bit shifts out of the master's shift register onto MOSI and one bit shifts in from MISO — and the slave does the mirror. Because there is no start bit, no parity, and no acknowledgement (unlike I²C or UART), the only thing keeping both ends aligned is the clock. So the protocol must nail down two timing decisions precisely:
- CPOL (Clock Polarity) — what logic level SCLK sits at when the bus is idle. CPOL=0 means SCLK idles low; CPOL=1 means it idles high.
- CPHA (Clock Phase) — which clock edge is the sampling edge. CPHA=0 samples on the first (leading) edge and drives data on the trailing edge; CPHA=1 drives on the leading edge and samples on the second (trailing) edge.
The leading edge is simply the first transition after chip-select asserts. If CPOL=0 the leading edge is a rising edge; if CPOL=1 it is a falling edge. CPHA is defined relative to that leading edge, not relative to "rising" or "falling" — this is the detail that trips up most engineers.
The four modes, concretely
Because CPOL and CPHA are each one bit, there are exactly four combinations. The table below is the one you will copy onto a sticky note:
| Mode | CPOL | CPHA | SCLK idle | Data sampled on | Data shifted on |
|---|---|---|---|---|---|
| 0 | 0 | 0 | Low | Rising edge | Falling edge |
| 1 | 0 | 1 | Low | Falling edge | Rising edge |
| 2 | 1 | 0 | High | Falling edge | Rising edge |
| 3 | 1 | 1 | High | Rising edge | Falling edge |
Mode 0 is the overwhelming default — most sensors (Bosch BME280, ADXL345, the vast majority of EEPROMs and flash like the Winbond W25Q series) power up expecting Mode 0. Mode 3 is the common second choice. Modes 1 and 2 are comparatively rare in practice.
Watching a bit travel: the sampling edge in motion
The abstract rule "sample on the leading edge" becomes obvious once you see it. In the animation below the receiver's sampling window (the glowing marker) snaps to each clock edge and latches whatever MOSI holds at that instant. Notice that the data line changes on the opposite edge from the one being sampled — this half-cycle of setup time is exactly what gives the receiver's input flip-flop a stable value to capture.
Matching a master to a slave datasheet
When a peripheral's datasheet gives you a timing diagram instead of a mode number, read it in two steps. First, look at SCLK before the first edge — if it sits high, CPOL=1; if low, CPOL=0. Second, look at where the first valid MOSI/MISO bit is relative to that first edge. If the first data bit is already valid before the first edge and is captured on it, that is CPHA=0. If data changes on the first edge and is captured on the second, that is CPHA=1. Combine the two bits and you have your mode.
In firmware this is one register field. On an STM32, SPI_CR1 exposes CPOL and CPHA bits directly; in Linux kernel drivers you set SPI_MODE_0..3 in spi_device.mode; in Arduino you call SPISettings(8000000, MSBFIRST, SPI_MODE0). The clock frequency, bit order (MSB vs LSB first), and CS polarity are independent knobs — a mode match alone does not guarantee success if, say, the slave expects MSB-first and you configured LSB-first.
A classic failure signature: every received byte is correct but shifted by one bit (e.g. you read 0x7F instead of 0xFF, or values that look "doubled"). That is almost always a CPHA mismatch — the receiver is latching half a clock early or late.
For verification, nothing beats capturing SCLK, MOSI, MISO and CS together on a logic analyzer (Saleae, or a sigrok-compatible unit) and letting its SPI decoder annotate bytes. At chip-design scale, the same waveforms are checked in simulation with protocol monitors written in SystemVerilog Assertions and driven by UVM agents under Synopsys VCS, Cadence Xcelium, or Siemens Questa — the verification engineer asserts that MOSI is stable across the sampling edge for the configured mode, catching a CPHA bug long before silicon.
Practical gotchas
- CPHA=1 and the first edge: in Mode 1 and Mode 3 the first clock edge drives rather than samples, so the slave must have its first bit ready one edge later. Some slaves need an extra dummy clock — check the datasheet.
- Chip-select timing: many slaves require CS to fall at least a setup time before the first SCLK edge, and will reset their internal bit counter if CS deasserts mid-byte. Keep CS asserted for the whole frame.
- Daisy-chaining: chained devices (e.g. multiple shift registers) must all share one mode; you cannot mix Mode 0 and Mode 3 devices on one SCLK.
- Clock speed vs. mode: raising SCLK frequency does not change the mode but shrinks the setup/hold margin, so a borderline wiring or level-shift issue may only appear at high speed.
If you want the broader picture of the four-wire bus, framing and CS management, read our companion guide SPI protocol explained, and for the next-door comparison see I²C vs SPI: choosing a serial bus. You can also explore the full hands-on track on our courses page. Engineers who need production verification of SPI IP often work with the design-services team at Avecas VLSI design services.
Ready to master embedded protocols? CourseTron's Embedded Systems track takes you from bit-banged SPI on an MCU to assertion-based protocol verification. Enroll today →
Frequently asked questions
How many SPI modes are there and why?
Exactly four, numbered 0 to 3. They are the four combinations of two binary settings — CPOL (clock idle polarity) and CPHA (sampling phase) — so 2 × 2 = 4 possibilities.
What is the difference between CPOL and CPHA?
CPOL sets the resting level of the clock line when idle; CPHA sets whether data is sampled on the first or second clock edge of each bit. CPOL affects the voltage at idle, CPHA affects timing within each bit period.
What happens if the master and slave use different SPI modes?
Data is sampled at the wrong instant, producing corrupted or bit-shifted bytes. The link may appear to "almost" work, which makes mode mismatches one of the most common and confusing SPI bugs.
Which SPI mode should I use by default?
Use Mode 0 (CPOL=0, CPHA=0) unless the peripheral's datasheet says otherwise — it is the most widely supported default across sensors, EEPROMs, and flash memory.