In short: The Raspberry Pi Pico exposes 26 usable 3.3 V GPIOs from the RP2040, each of which can be muxed to UART, SPI, I2C, PWM, PIO or a clock function, with four pins doubling as ADC inputs, so reading the pinout is really reading a function-select table rather than a fixed pin list.
The 40 pins at a glance
The Pico board has 40 castellated pins at a 2.54 mm pitch. Of those, 8 are ground, and the remainder split into power (VBUS pin 40, VSYS pin 39, 3V3 OUT pin 36, 3V3_EN pin 37, ADC_VREF pin 35), the RUN reset pin (30), and the GPIOs. The RP2040 itself has 30 GPIOs (GP0 to GP29), but GP23, GP24 and GP25 never reach the header: on the Pico they drive the SMPS power-save mode, VBUS detect and the green LED. GP29 is wired to VSYS through a divider, which leaves GP0-GP22 plus GP26-GP28 as the 26 you can use.
All GPIO is 3.3 V and not 5 V tolerant. Feeding a 5 V sensor output directly into a pin is the most common way to kill one. Use a divider or a level shifter.
Key fact: GP23, GP24 and GP25 exist on the RP2040 but are used internally on the Pico (SMPS mode, VBUS sense, LED). Pico W moves the LED behind the wireless chip, so code that blinks GP25 breaks there.
GPIO and the function-select mux
Every pad has a 5-bit FUNCSEL field in its IO_BANK0 control register. The options per pin are numbered: F1 SPI, F2 UART, F3 I2C, F4 PWM, F5 SIO (plain software GPIO), F6 and F7 the two PIO blocks, F8 clocks/GPIN/GPOUT, F9 USB. That is why you can put UART0 on GP0/1, GP12/13 or GP16/17: the peripheral is fixed, the pad routing is not, within the datasheet's allowed pin sets.
Each pad also has a configurable drive strength (2, 4, 8 or 12 mA), slew rate, Schmitt trigger input, and pull-up/pull-down. The default is 4 mA, and the sum across the chip should stay well below the supply limits, so a bare GPIO cannot drive a motor or a relay. The pads are SIO-controlled when F5 is selected, and the single-cycle IO block lets the cores toggle a pin in one clock, roughly 8 ns at 125 MHz.
ADC: four pins, five channels
The ADC is a 12-bit successive-approximation converter clocked from the 48 MHz USB clock. A conversion takes 96 cycles, giving 500 ksps. Inputs: GP26, GP27, GP28 (ADC0 to ADC2), GP29 (ADC3, tied to VSYS/3 on Pico) and an internal temperature diode as channel 4.
- LSB size is 3.3 V / 4096, about 0.8 mV.
- The datasheet quotes an effective resolution closer to 8.7 bits because of supply noise and DNL errors (erratum E11 shows missing codes near 512, 1536, 2560 and 3584).
- Reference is ADC_VREF (pin 35), which on the stock board is just a filtered 3V3. For better accuracy, feed an external 3.0 V reference and add an RC filter to ADC_VREF.
Only one conversion runs at a time. A round-robin mask lets the ADC cycle through channels and push results into a 4-sample FIFO that a DMA channel can drain, so you can log a signal without CPU involvement.
PWM slices: the mapping interviewers ask about
The RP2040 has 8 PWM slices, each with two output channels (A and B), so 16 independent outputs. Each slice owns one 16-bit counter with a shared wrap value and an 8.4 fixed-point clock divider (1.0 to 255.9375). The two channels share a frequency but have separate compare levels, so duty cycles differ and frequencies cannot.
The mapping is mechanical: slice = (gpio / 2) % 8 and channel = gpio % 2 (0 = A, 1 = B). GP0 is slice 0 A and GP1 is slice 0 B, but GP16 and GP17 also land on slice 0, because 16 / 2 = 8 and 8 % 8 = 0. Two pins on the same slice and channel receive the same signal. Connecting GP0 and GP16 as independent outputs is a classic bug.
| GPIO | Slice | Channel |
|---|---|---|
| GP0 / GP16 | 0 | A |
| GP1 / GP17 | 0 | B |
| GP14 / GP30* | 7 | A |
| GP15 | 7 | B |
| GP25 (LED) | 4 | B |
Frequency = f_sys / (div × (wrap + 1)). For a 20 kHz motor drive: div 1, wrap 6249 gives 125 MHz / 6250 = 20 kHz, with 6250 duty steps (about 12.6 bits). For a 50 Hz servo: div 64, wrap 39062 gives 125 MHz / 64 / 39063 = 50 Hz, and a 1.5 ms pulse is level 2930.
gpio_set_function(15, GPIO_FUNC_PWM);
uint slice = pwm_gpio_to_slice_num(15); // 7
pwm_set_clkdiv(slice, 64.0f);
pwm_set_wrap(slice, 39062);
pwm_set_chan_level(slice, PWM_CHAN_B, 2930);
pwm_set_enabled(slice, true);Key fact: The two channels of a slice share one counter. Change the wrap value and both outputs change frequency together; only the compare levels are independent.
UART, SPI and I2C mapping
There are two of each peripheral, and each signal has several candidate pins. Defaults in the Pico SDK are UART0 on GP0/GP1, UART1 on GP8/GP9, I2C0 on GP4/GP5, I2C1 on GP6/GP7, SPI0 on GP16 (RX), GP18 (SCK) and GP19 (TX), and SPI1 on GP12 (RX), GP14 (SCK) and GP15 (TX).
- UART: up to several Mbaud with a 32-entry-deep 8-bit FIFO and hardware flow control on the CTS/RTS pins. It is a PL011 clone.
- I2C: DesignWare core, standard (100 kHz), fast (400 kHz) and fast-plus (1 MHz). The internal pull-ups are about 50 to 80 kohm, far too weak, so add 4.7 kohm externally.
- SPI: PL022 core, Motorola, TI or Microwire frames, 4 to 16 bit words, and up to roughly 62.5 MHz as a master from a 125 MHz peripheral clock.
A frequent mistake is assuming that any two pins can be used. You must choose from the legal set: SDA must be on a pin whose F3 function is I2Cx SDA. The SDK's gpio_set_function will not warn you.
PIO: eight tiny state machines
The Programmable I/O block is what makes the RP2040 different from a typical Cortex-M0+ part. There are two PIO blocks, each with four state machines (8 total), sharing 32 instruction words per block. Each state machine has its own pair of 4-word FIFOs (joinable into one 8-word FIFO), two 32-bit shift registers (ISR and OSR), scratch registers X and Y, a program counter and a fractional clock divider.
The instruction set has only nine opcodes (JMP, WAIT, IN, OUT, PUSH, PULL, MOV, IRQ, SET), and every instruction executes in exactly one cycle, with optional side-set and delay bits. This deterministic timing is how people build WS2812 LED drivers (800 kHz, 1.25 us bit time), DVI/VGA output, I2S audio, extra UARTs, and even logic analysers on a $4 board. At 125 MHz, one cycle is 8 ns, so a WS2812 bit of 10 cycles at an 8 MHz PIO clock is exactly 1.25 us.
Key fact: PIO instructions are single-cycle and fully deterministic, so jitter is zero on a PIO-driven pin. That is why bit-banged protocols in PIO run reliably even while both Cortex cores are busy or asleep.
Design notes that matter in practice
- Plan pins on paper first: PWM slice conflicts and shared SPI/I2C routes are discovered late otherwise. For custom boards, Cadence Allegro or Siemens Xpedition handle the pin-swap constraints, and the RP2040's flexible mux makes routing easier than on most MCUs.
- Decouple the ADC: keep GP26-GP28 signals away from the 3V3 SMPS noise, and drive GP23 high to force PWM mode, which cuts ripple, if ADC accuracy matters.
- Give the SWD pads (SWCLK, SWDIO, GND) on the underside a test header, since they let a debugger program the part without the BOOTSEL button.
For how the two cores, the bus fabric and the memory map tie these peripherals together, see the RP2040 architecture walkthrough, and for interfacing sensors over I2C look at I2C protocol explained. Teams who want to take such a design to a custom board can talk to Avecas design services.
Want to go from pin tables to working firmware and silicon-level understanding? Explore the embedded and VLSI tracks in our CourseTron courses.
FAQ
How many usable GPIO pins does the Pico have?
26: GP0 to GP22 and GP26 to GP28. GP23 to GP25 are used by on-board power control, VBUS detect and the LED, and GP29 measures VSYS.
Can I use any pin for I2C or SPI?
No. Each signal can only appear on a specific set of pads. SDA must be on a pin with the I2C SDA function for that controller. PIO is the exception, since it can drive almost any pin.
How many PWM outputs can run at different frequencies?
Eight, one per slice. The two channels of a slice share a counter and therefore a frequency, though their duty cycles are independent.
Are Pico GPIOs 5 V tolerant?
No. They are 3.3 V only. Use a resistor divider or level shifter on inputs from 5 V logic.