Shift Register

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In short: A shift register is a chain of D flip-flops sharing one clock, where each flop's output feeds the next flop's input, so every clock edge moves the stored bits exactly one position and lets you convert between serial and parallel data, delay signals, and build scan chains and pseudo-random generators.

What a shift register actually is

Take N edge-triggered D flip-flops, connect them to the same clock, and wire the Q output of each one to the D input of the next. That is the whole circuit. On every active clock edge, flop 0 captures the external serial input, flop 1 captures what flop 0 held a moment earlier, flop 2 captures flop 1's old value, and so on. The pattern slides along the chain one place per clock, which is why the structure is also called a delay line: a bit entered at the input appears at the output exactly N clock cycles later.

The reason this works is edge-triggering. All flops sample their inputs at the same instant, and each output only changes after the clock-to-Q delay. Every flop therefore sees the old value of its predecessor. If you used level-sensitive latches with an overlapping enable, the first bit would race through the whole chain in a single phase, which is the classic "race-through" failure interviewers love to ask about.

Each flop's Q drives the next flop's D. One shared clock moves every bit one stage per edge.

Walking through a 4-bit example

Start from 0000 and feed the serial stream 1, 0, 1, 1 (first bit first). After clock edge 1 the register holds Q0Q1Q2Q3 = 1000. After edge 2 it holds 0100, after edge 3 it holds 1010, and after edge 4 it holds 1101. Notice that the first bit sent ended up in the last flop, Q3. Four clocks have converted a serial stream into a 4-bit parallel word that you can read from all four outputs at once.

After four edges the outputs read Q0..Q3 = 1,1,0,1. The staircase of delayed copies is the signature of a shift register.

Key fact: An N-bit serial-in shift register needs N clock cycles to load, but only one clock cycle to read all N bits in parallel, which is why it is the standard serial-to-parallel converter.

The four data-movement modes

Shift registers are named by how data enters and leaves. The hardware is the same chain; only the I/O differs.

Type	Load	Read	Typical use
SISO	1 bit per clock	1 bit per clock	Digital delay line, N-cycle latency
SIPO	1 bit per clock	All bits at once	UART receiver, LED/GPIO expanders like the 74HC595
PISO	All bits at once (load pin)	1 bit per clock	UART transmitter, 74HC165 input expansion
PIPO	All bits at once	All bits at once	Plain storage register

A PISO needs a multiplexer in front of every D input: one choice is the previous stage's Q (shift), the other is the parallel data bit (load). A control line, often called SHIFT/LOAD, picks between them. Add a direction input and a hold option and you get the generalized device covered in our universal shift register article.

See it move

A single logic 1 hops one flop to the right every clock edge, then the loop restarts.

Timing: where shift registers really break

Setup is rarely the problem. With zero logic between flops, the minimum clock period is roughly t_clk-to-Q + t_setup + skew. For a typical 28 nm library with t_cq near 0.15 ns and t_setup near 0.05 ns, a bare chain could in principle run at several GHz. The real danger is hold time.

Hold requires that the new value from the previous flop does not arrive before the capturing flop has finished sampling: t_cq + t_wire ≥ t_hold + t_skew. In a shift register the data path is just a wire, so the margin is only t_cq minus t_hold minus skew. If the clock reaches flop 2 about 100 ps later than flop 1, and t_cq is 150 ps with 30 ps hold, the margin shrinks to 20 ps and any extra skew corrupts data: the bit "double-shifts" through two stages. Raising the clock frequency does not fix a hold violation, which is a favourite trick question.

Physical-design tools such as Synopsys IC Compiler II and Cadence Innovus repair this by inserting delay buffers on the data wire during hold fixing. When the clock domains differ in a scan chain, designers also insert a lockup latch, a latch transparent on the clock's low phase, between the two domains so the data is held safely across the skew.

Key fact: Hold violations in back-to-back flops are independent of clock frequency. They are fixed by adding delay or reducing skew, never by slowing the clock.

Real applications

Serial communication: UART, SPI and I2S all rely on SIPO and PISO registers to turn byte-wide bus data into a bit stream and back. An 8-bit SPI transfer at 10 MHz takes 800 ns.
I/O expansion: A 74HC595 gives eight outputs for three microcontroller pins, and daisy-chained devices form one long register.
Scan chains for DFT: Test tools like Synopsys DFT Compiler and Siemens Tessent replace ordinary flops with scan flops (a mux plus a D flop) and stitch them into shift registers, so a tester can shift in a pattern, pulse the functional clock once, and shift the response out.
Synchronizers: A two-flop clock-domain synchronizer is a 2-bit shift register whose second stage gives metastability time to resolve.
LFSRs: Feed back an XOR of selected taps into the input and an N-bit register cycles through up to 2^N−1 states. This is used for CRC, scramblers and BIST pattern generation; the topic continues in our ring and Johnson counter article.

Writing it in RTL

In Verilog, the non-blocking assignment makes every flop sample the old values, which models the hardware correctly:

always @(posedge clk or negedge rst_n)
  if (!rst_n) sr <= 4'b0000;
  else        sr <= {sr[2:0], sin};   // shift left, new bit enters LSB
assign sout = sr[3];

Using blocking assignments (=) in a chain of separate always blocks creates simulation races, and synthesis may then collapse your register into a single flop. If you need a long delay, say 64 or more cycles, a synthesis tool or FPGA flow will infer a shift-register primitive such as Xilinx SRL16/SRL32, which is much cheaper than discrete flops but has no reset on intermediate stages. Mention that trade-off in an interview and you will stand out.

To practise these flows end to end, from RTL through scan insertion and hold fixing, see the hands-on tracks at ChipXpert VLSI training, and browse the structured paths in our CourseTron courses.

Key fact: Use non-blocking assignments for sequential logic. The right-hand sides are all evaluated before any flop updates, which is exactly how real edge-triggered hardware behaves.

Ready to go deeper? Join the Digital Electronics course on CourseTron for timing labs, waveform exercises and interview-style questions on shift registers, counters and FSMs.

Frequently asked questions

Why does a shift register use edge-triggered flops instead of latches?

Latches are transparent during an entire clock level, so a bit could travel through several stages in one phase. Edge-triggered flops sample only at the instant of the edge, guaranteeing one stage of movement per clock.

How many clock cycles does it take to load and read an 8-bit SIPO register?

Eight clock cycles to shift in all eight bits. After that, the full byte is available in parallel on the outputs immediately, with no further clocks needed.

Can a shift register hold a hold-time violation even at low frequency?

Yes. Hold depends on the data path delay versus clock skew and flop hold time, not on the period. Fix it with delay buffers or by balancing the clock tree.

What is the difference between a shift register and a counter?

A shift register moves existing bits sideways with no arithmetic. A counter changes its state by combinational next-state logic. Ring and Johnson counters are shift registers with feedback, which is where the two ideas meet.