In short: A multiplexer is a digitally controlled switch that passes one of several inputs to a single output, which makes it the workhorse for data routing, parallel-to-serial conversion, implementing arbitrary Boolean functions and building shared buses.
1. What a multiplexer really computes
A 2n:1 multiplexer (mux) has 2n data inputs, n select lines and one output. For a 4:1 mux the output is Y = S1'S0'·I0 + S1'S0·I1 + S1S0'·I2 + S1S0·I3. Each select combination is a minterm that "enables" exactly one data input, so the mux is simply a decoder feeding an AND-OR plane. In CMOS, a mux is usually built from transmission gates, which is why a 2:1 mux cell in a 7 nm or 28 nm library is often smaller and faster than the equivalent NAND-NAND version.
2. Data routing and source selection
The most common use is choosing between sources. Inside a CPU datapath, a 2:1 mux in front of the ALU decides whether operand B is a register value or a sign-extended immediate; a mux after the ALU picks between the ALU result and a load from memory (the write-back stage). A 32-bit datapath mux is simply 32 parallel copies of a 1-bit mux sharing one select line, so the select signal has a fanout of 32 and often needs buffering during synthesis.
Clock selection is a subtler routing case. A clock mux that switches between two asynchronous clocks can glitch if the select changes while the chosen clock is high, creating a runt pulse. Production designs use glitch-free clock multiplexers with synchronised, negative-edge-latched selects, and tools such as Synopsys PrimeTime flag unsafe clock-mux topologies during clock-gating checks.
Key fact: An N-input mux needs ceil(log2 N) select lines, so a 64:1 mux needs just 6 selects, but its delay grows roughly with log N when built as a tree of 2:1 muxes.
3. Parallel-to-serial conversion
Connect an 8:1 mux to a 3-bit binary counter and feed the counter into the select pins. As the counter steps 000, 001, ..., 111, the mux outputs D0, D1, ..., D7 in sequence: an 8-bit word leaves on a single wire in eight clock cycles. This is the combinational heart of a parallel-in serial-out (PISO) transmitter. Compared with a shift register it needs no per-bit load logic, and the data word can be held stable while it is read out.
The trade-off is throughput. Sending 8 bits serially needs a serial clock 8x faster than the word rate; for a 100 MHz word rate that is 800 Mb/s on the pin. High-speed SerDes transmitters push this idea to the extreme with a final 2:1 mux running at the full line rate, built from carefully matched current-mode logic, to interleave two half-rate data streams. The animation below shows the counter sweeping across the data word.
4. Implementing logic functions with muxes
Because a mux is a universal element, any n-variable function can be implemented with a 2n:1 mux by wiring the variables to the selects and tying inputs to 0 or 1 from the truth table. Better still, Shannon expansion lets you use a 2n-1:1 mux: n-1 variables drive the selects, and the data inputs are 0, 1, the last variable, or its complement.
Take F(A,B,C) = Σm(1, 2, 6, 7). Use A and B as selects of a 4:1 mux. For AB=00 only minterm 1 is true, so F = C. For AB=01 only minterm 2 is true, so F = C'. For AB=10 nothing is true, so F = 0. For AB=11 both minterms are true, so F = 1. One 4:1 mux and one inverter replace a sum-of-products network.
This is not just a classroom trick. An FPGA lookup table (LUT) is exactly a mux tree: a 6-input LUT in a Xilinx or Intel device is a 64:1 mux whose data inputs are SRAM configuration bits and whose selects are your six logic signals. When Vivado or Quartus maps your RTL, it is choosing the 64 stored bits.
| Function size | Direct mux | With Shannon reduction |
|---|---|---|
| 2 variables | 4:1 | 2:1 |
| 3 variables | 8:1 | 4:1 |
| 4 variables | 16:1 | 8:1 |
Key fact: An n-variable function always fits in a 2n-1:1 mux plus at most one inverter, because every data input is one of 0, 1, X or X'.
5. Bus systems and shared lines
A bus is a set of wires shared by several sources. There are two implementations. Older board-level buses used tri-state drivers: only one driver is enabled, the others float at high impedance. On-chip designs mostly avoid internal tri-states because of contention risk and poor timing analysis; instead, a wide mux selects which block drives the read-data bus. AXI and AHB interconnects, for example, use a read-data multiplexer controlled by the decoded address of the active slave, and an arbiter provides the select.
- Register-file read ports: a 32-entry, 64-bit register file has one 32:1 mux per read port bit, so a dual-read-port file contains 128 such muxes.
- Bidirectional pads: a mux (or enable) decides whether the pad is driven by the core or listened to.
- Memory addressing: column muxes in an SRAM pick one bitline pair out of 4, 8 or 16 per sense amplifier.
If you want the reverse operation, where one source fans out to many destinations, read our guide to demultiplexer applications. Selecting among many sources is also the foundation of encoders and priority logic.
6. Timing, glitches and synthesis pitfalls
Interviewers love two questions. First, can a mux glitch? Yes: a 2:1 mux built as Y = S'A + SB produces a static-1 hazard when A = B = 1 and S toggles, because S' lags S through the inverter. Adding the consensus term AB removes it, and standard cells in Cadence Genus or Synopsys Design Compiler libraries are characterised to avoid this internally. Second, why does an unintended mux appear in your netlist? An incomplete case or if without an else creates a latch; a fully specified one infers a mux.
assign y = sel[1] ? (sel[0] ? d3 : d2)
: (sel[0] ? d1 : d0);Logic synthesis balances such trees automatically, but verification still matters: simulate exhaustively in Siemens Questa or Synopsys VCS for small muxes, and use formal equivalence checking for wide ones. For physical design teams, Avecas design services routinely review mux-heavy datapaths for timing closure. If you want structured practice, ChipXpert VLSI training covers these flows hands on.
Ready to master combinational design with labs and interview drills? Explore the digital electronics tracks in the CourseTron courses and start building real mux-based circuits today.
Frequently Asked Questions
How many select lines does a 16:1 multiplexer need?
Four, because 24 = 16. In general an N:1 mux needs log2(N) select bits.
Can a multiplexer implement any logic gate?
Yes. A 2:1 mux with inputs 0 and B and select A gives AND; inputs B and 1 give OR; inputs 1 and 0 with select A give NOT. This is why muxes are called universal.
What is the difference between a mux and a demux?
A mux selects one of many inputs for a single output; a demux routes a single input to one of many outputs. They are used as a pair in time-division multiplexed links.
Why avoid tri-state buses inside chips?
Tri-states risk bus contention and floating nodes, and they complicate static timing and scan testing. A mux-based bus is fully static and easy to analyse.