SAR vs sigma-delta ADC

In short: SAR ADCs win when you need fast, per-sample conversions at moderate resolution (10–18 bits, kSPS–MSPS); sigma-delta ADCs win when you need very high resolution (20–32 bits) at lower bandwidth by trading speed for oversampling and noise shaping.

Pick the wrong ADC architecture and you either burn power chasing bits you cannot use, or you starve a precision measurement of the resolution it needs. The two workhorses of the integrated-ADC world — the successive-approximation register (SAR) and the sigma-delta (ΣΔ) converter — sit at opposite ends of the speed/resolution plane, and understanding why is one of the most common analog interview questions. This article walks through the mechanisms, the math behind oversampling and noise shaping, and where each architecture actually ships.

The core tradeoff: one sample at a time vs. averaging the truth

A SAR ADC is a binary search. For an N-bit converter it performs N comparator decisions per sample, each time driving a capacitive DAC to halve the remaining uncertainty. A 16-bit SAR therefore needs 16 compare cycles plus acquisition — fast, deterministic latency, and essentially zero pipeline delay. That makes it ideal for multiplexed, event-driven sampling.

A sigma-delta ADC does the opposite. A crude (often 1-bit) quantizer runs far faster than the output data rate, and a digital decimation filter averages thousands of those coarse samples into one high-resolution word. The resolution is built up statistically over time, not resolved bit-by-bit in a single shot.

Rule of thumb: SAR dominates 100 kSPS–10 MSPS at 12–18 bits; sigma-delta dominates DC–1 MHz bandwidth at 18–32 bits. Where they overlap (~16–18 bits, ~100 kSPS) the decision comes down to latency, channel count, and power budget.

Oversampling: buying bits with sample rate

Quantization noise from an ideal N-bit converter is spread roughly uniformly across the Nyquist band (0 to f_s/2). If you sample K times faster than needed and then digitally low-pass filter back to the band of interest, you discard most of that noise power. The classic result: each 4× in oversampling ratio (OSR) buys one extra bit of resolution (6 dB SNR) — but only with a flat-noise converter. For a plain Nyquist ADC this is an expensive way to gain bits.

Plain oversampling alone: SNR improves ~3 dB per octave of OSR (½ bit per 2×). Noise shaping is what makes sigma-delta efficient — it steepens that slope dramatically.

Noise shaping: the sigma-delta superpower

A sigma-delta modulator puts the quantizer inside a feedback loop with an integrator. The loop's transfer function passes the signal flat but high-pass-filters the quantization noise, pushing it out of the low-frequency band where your signal lives. The decimation filter then throws that out-of-band noise away.

For an L-order modulator the in-band SNR improves by (6L+3) dB per octave of OSR. A 2nd-order loop at OSR=256 can deliver 20+ effective bits from a single-bit quantizer. This is why precision instrumentation uses ΣΔ: the analog front end is simple and the heavy lifting is digital, where it scales with process nodes. The flip side is latency — the decimation filter settles over many cycles, so a channel switch costs several conversion periods.

Head-to-head comparison

Where each one ships

SARs are everywhere data acquisition is multiplexed or latency-critical: motor-control current sensing, portable instruments, battery monitoring, LIDAR, and the analog inputs on most microcontrollers. Think Analog Devices AD4000-series or TI ADS8xxx parts at 1 MSPS / 16–18 bits.

Sigma-deltas own precision and slow-but-exact domains: weigh scales and load cells, thermocouple/RTD temperature measurement, energy metering, ECG/EEG biopotential front ends, and seismic/vibration sensing. Audio codecs are almost universally ΣΔ because the band is narrow (20 kHz) and 100+ dB SNR is required.

Designing or verifying either core in a modern flow leans on the usual EDA stack — Cadence Spectre/Virtuoso for the analog modulator and comparator, Synopsys for the decimation-filter RTL and DFT, and Siemens (Questa/Calibre) for mixed-signal verification and sign-off. If you want to go deeper on the full landscape, see our guide to ADC architectures and the companion piece on ENOB, SNR and effective resolution. For hands-on mixed-signal design mentoring, our partner Avecas VLSI design services runs industrial tape-out flows.

Want to master analog data converters end-to-end — from cap-DAC sizing to SNDR budgets and decimation-filter design? Explore CourseTron's analog and mixed-signal track on our courses page and build interview-ready depth.

Frequently asked questions

Can a sigma-delta ADC ever be faster than a SAR?

For raw sample throughput, no — the modulator must run at OSR times the output rate, so a ΣΔ needs a very high internal clock to reach even moderate output bandwidth. High-speed ΣΔ parts exist (continuous-time designs in RF), but for general-purpose MSPS sampling the SAR is the natural fit.

Why is a 1-bit quantizer enough for 24-bit output?

Resolution is created in time, not in a single comparison. Noise shaping plus decimation averages millions of 1-bit decisions per second; the feedback loop keeps the average of the bitstream equal to the input, and the filter resolves that average to many bits. A 1-bit quantizer is also inherently linear, which protects overall accuracy.

What is ENOB and why does it matter more than the datasheet bit count?

ENOB (effective number of bits) is derived from measured SINAD: ENOB = (SINAD − 1.76)/6.02. A part labeled 24-bit may deliver only 21 ENOB once thermal and quantization noise are included, so always design to ENOB, not the nominal word width.

Which should I pick for a 4-channel temperature logger?

If you can tolerate per-channel settling, a sigma-delta gives you the 20+ bits RTD/thermocouple measurement wants. If you must scan all four channels fast and simultaneously-ish, a multiplexed SAR (or one SAR per channel) avoids the ΣΔ settling penalty.